Method and arrangement for setting an effective resolution of an output signal in incremental delta-sigma analog-to-digital converters
A method and arrangement for setting an effective resolution of an output signal in an incremental delta-sigma analog-to-digital conversion by an incremental delta-sigma analog-to-digital converter, includes feeding a difference between an input signal and a reference voltage signal formed in a feedback branch to a first integrator. Safeguarding the stability of multi-stage incremental delta-sigma analog-to-digital converters for large input signal ranges and not requiring direct damping of the input signal, such that a direct SNR impairment with regard to the ADC-inherent noise sources can be avoided, is achieved by a virtual reference voltage in the feedback branch of the incremental delta-sigma analog-to-digital converter. The reference voltage signal is adapted to a changing input signal range by a settable reference capacitance and a clock cycle number dependent thereon is set.
1. A method for setting an effective resolution of an output signal in an incremental delta-sigma analog-to-digital conversion by an incremental delta-sigma analog-to-digital converter, comprising: feeding a difference between an input signal and a reference voltage signal formed in a feedback branch to a first integrator, forming a virtual reference voltage in the feedback branch of the incremental delta-sigma analog-to-digital converter, adapting the reference voltage signal to a changing input signal range with a settable reference capacitance, and settling a clock cycle number N dependent thereon.
2. The method according to claim 1 , wherein the reference capacitance is adapted and set by a controllable capacitance array.
3. The method according to claim 1 , wherein selection of the reference capacitance and the setting of the clock cycle number N are carried out in such a way that the input signal in a range of an operating voltage of +/−V DD , modulates the incremental delta-sigma analog-to-digital converter to a maximum possible extent in a manner free of overdriving.
4. The method according to claim 2 , wherein the reference capacitance and the clock cycle number N are set by a control unit.
5. The method according to claim 4 , wherein the control unit controls at least two integrator stages of the incremental delta-sigma analog-to-digital converter, a quantizer and a digital-to-analog converter in the feedback branch.
6. The method according to claim 4 , wherein the control unit determines and sets an optimum clock cycle number according to a required accuracy range of the incremental delta-sigma analog-to-digital converter, the set reference capacitance or further to incremental delta-sigma analog-to-digital converter inherent measurement values dependent algorithm.
7. The method according to claim 1 , wherein a single incremental delta-sigma analog-to-digital converter is used for multiplexed systems.
8. The method according to claim 1 , wherein the incremental delta-sigma analog-to-digital converter is adapted to an accuracy requirement with regard to effective resolution of an output signal.
9. An arrangement for incremental delta-sigma analog-to-digital conversion, wherein the incremental delta-sigma analog-to-digital converter comprises a difference forming unit for forming a difference between an analog modulator input signal and an analog reference voltage signal and for generating a difference voltage signal, a resettable first integrator for integrating or summing the difference signal and generating a first integrator signal, a quantizer for receiving the integrator signal and generating a digital quantization signal, and a digital-to-analog converter in a feedback branch for receiving the digital quantization signal and outputting the reference voltage signal to the difference forming unit, wherein a controllable capacitance array is arranged in the feedback branch, and wherein the capacitance array, at least one integrator, the quantizer and the digital-to-analog converter in the feedback branch are connected to a control unit in a controlling fashion.
10. The arrangement for incremental delta-sigma analog-to-digital conversion according to claim 9 , wherein the incremental delta-sigma analog-to-digital converter has a number of integrator stages.
11. The arrangement for incremental delta-sigma analog-to-digital conversion according to claim 9 , wherein an input signal in a range of an operating voltage of +/−V DD of the incremental delta-sigma analog-to-digital converter is fully modulatable independently of the number of integrator stages.
12. The arrangement for incremental delta-sigma analog-to-digital conversion according to claim 9 , wherein the control unit comprises a clock control logic.