IP Library Granted Patent US 9,837,493
Granted Patent B2
US 9,837,493 · App. 14/940,867 · Granted Dec 5, 2017

Semiconductor device and method for fabricating the same

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Quick Facts
Patent No.
US 9,837,493
App. No.
14/940,867
Granted
Dec 5, 2017
Kind
B2
Abstract

A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

Claims (12)

1. A semiconductor device, comprising:

a semiconductor substrate, having an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface; and

a semiconductor fin, disposed in the recess and extending upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess;

wherein the semiconductor fin comprises a material other than that used to constitute the semiconductor substrate, and the material other than that used to constitute the semiconductor substrate has a germanium (Ge) concentration gradually decreased from a bottom surface of the recess to the upper surface.

2. The semiconductor device according to claim 1 , wherein the recess has a bottom surface; and the semiconductor hetero-interface has a dislocation occurring between two levels respectively parallel to the bottom surface and the upper surface.

3. The semiconductor device according to claim 2 , wherein the semiconductor substrate comprises silicon.

4. The semiconductor device according to claim 2 , wherein the semiconductor fin comprises:

a first portion, disposed on the semiconductor substrate, extending into the recess and forming the semiconductor hetero-interface with the semiconductor substrate; and

a second portion, disposed on the first portion and including a semiconductor material that is different from that used to constitute the first portion.

5. The semiconductor device according to claim 2 , wherein the recess has a depth substantially ranging from 20 nm to 80 nm, and the semiconductor fin has an aspect ratio substantially ranging from 10 to 20.

6. The semiconductor device according to claim 1 , wherein the recess shapes as a bowl or a polyhedron or has an irregular shape.

7. The semiconductor device according to claim 1 , further comprises a dielectric layer having a trench substantially aligning the recess and allowing the semiconductor fin formed therein.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2015
From: CHEN, CHIEN-HUNG; HUANG, SHIH-HSIEN; YANG, YU-RU; CHIANG, HUAI-TZU; LEE, HAO-MING; LIN, SHENG-HAO; TSAI, CHENG-TZUNG; WU, CHUN-YUAN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 037037/0024 →