Vector load with instruction-specified byte count less than a vector size for big and little endian processing

1. A method for loading a vector with a processor, the method comprising:

obtaining, by the processor, a variable-length vector load instruction that comprises (i) a TX field, (ii) a T field, (iii) an RA field specifying a general purpose register address specification for a memory address, (iv) an RB field specifying a length of the general purpose register address specification, and (v) one or more fields identifying the variable-length vector load instruction, wherein at least two ranges of vector registers for a target are available, wherein each of the at least two ranges of vector registers for the target is controlled by a respective one or more bits in a machine state register;

selecting one of the at least two ranges of vector registers for the target, based on the TX field within the variable-length vector load instruction;

selecting a vector register for the target within the selected range of vector registers for the target, based on the T field within the variable-length vector load instruction;

determining whether data should be loaded into the vector register using big endian byte-ordering or little endian byte-ordering;

loading data from memory into the vector register by

iteratively fetching load data for each of a plurality of addresses in the variable-length vector load instruction, wherein each iteration of a load data fetch comprises:

fetching load data for an address in the variable-length vector load instruction;

placing the fetched load data in the vector register according to big endian byte-ordering or little endian byte-ordering; and

proceeding to access a next address in the variable-length vector load instruction;

determining a length of the fetched load data for all of the plurality of addresses is less than a length of the vector register; and

iteratively setting one or more residue bytes in the vector register to a pad value, wherein each iteration of setting the one or more residue bytes comprises:

setting a first residue byte of the one or more residue bytes to the pad value according to big endian byte-ordering or little endian byte-ordering; and

proceeding to a next residue byte of the one or more residue bytes.

2. The method of claim 1 , wherein data is loaded in leftmost bytes responsive to a determined first byte-ordering, and data is loaded in rightmost bytes responsive to a determined second byte ordering.

3. The method of claim 1 , wherein the pad value is zero.

4. The method of claim 1 , wherein loading data from memory into the vector register further comprises:

retrieving data from memory, wherein the data retrieved is determined by the memory address and the length; and

storing the retrieved data in the vector register based on the determined byte-ordering.

5. The method of claim 1 , wherein the length is specified in a portion of the bits in the general purpose register.

6. A computer program product, comprising:

a non-transitory computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code configured to perform an operation for loading a vector with a processor, the operation comprising:

obtaining, by the processor, a variable-length vector load instruction that comprises (i) a TX field, (ii) a T field, (iii) an RA field specifying a general purpose register address specification for a memory address, (iv) an RB field specifying a length of the general purpose register address specification, and (v) one or more fields identifying the variable-length vector load instruction, wherein at least two ranges of vector registers for a target are available, wherein each of the at least two ranges of vector registers for the target is controlled by a respective one or more bits in a machine state register;

selecting one of the at least two ranges of vector registers for the target, based on the TX field within the variable-length vector load instruction;

selecting a vector register for the target within the selected range of vector registers for the target, based on the T field within the variable-length vector load instructions;

determining whether data should be loaded into the vector register using big endian byte-ordering or little endian byte-ordering;

loading data from memory into the vector register by: iteratively fetching load data for each of a plurality of address in the variable-length vector load instruction, wherein each iteration of a load data fetch comprises:

fetching load data for an address in the variable-length vector load instruction;

placing the fetched load data in the vector register according to big endian byte-ordering or little endian byte-ordering; and

proceeding to access a next address in the variable-length vector load instruction;

determining a length of the fetched load data for all of the plurality of addresses is less than a length of the vector register; and

iteratively setting one or more residue bytes in the vector register to a pad value, wherein each iteration of setting the one or more residue bytes comprises:

setting a first residue byte of the one or more residue bytes to the pad value according to big endian byte-ordering or little endian byte-ordering; and

proceeding to a next residue byte of the one or more residue bytes.

7. The computer program product of claim 6 , wherein data is loaded in leftmost bytes responsive to a determined first byte-ordering, and data is loaded in rightmost bytes responsive to a determined second byte ordering.

8. The computer program product of claim 6 , wherein the pad value is zero.

9. The computer program product of claim 6 , wherein loading data from memory into the vector register further comprises:

retrieving data from memory, wherein the data retrieved is determined by the memory address and the length; and

storing the retrieved data in the vector register based on the determined byte-ordering.

10. The computer program product of claim 6 , wherein the length is specified in a portion of the bits in the general purpose register.

11. A system, comprising:

a processor; and

a memory storing a program, which, when executed on the processor, performs an operation for loading a vector, the operation comprising:

obtaining, by the processor, a variable-length vector load instruction that comprises (i) a TX field, (ii) a T field, (iii) an RA field specifying a general purpose register address specification for a memory address, (iv) an RB field specifying a length of the general purpose register address specification, and (v) one or more fields identifying the variable-length vector load instruction, wherein at least two ranges of vector registers for a target are available, wherein each of the at least two ranges of vector registers for the target is controlled by a respective one or more bits in a machine state register;

selecting one of the at least two ranges of vector registers for the target, based on the TX field within the variable-length vector load instruction;

selecting a vector register for the target within the selected range of vector registers for the target, based on the T field within the variable-length vector load instruction;

determining whether data should be loaded into the vector register using big endian byte-ordering or little endian byte-ordering;

loading data from memory into the vector register by: iteratively fetching load data for each of a plurality of address in the variable-length vector load instruction, wherein each iteration of a load data fetch comprises:

fetching load data for an address in variable-length vector load instruction;

placing the fetched load data in the vector register according to big endian byte-ordering or little endian byte-ordering; and

proceeding to access a next address in the variable-length vector load instruction;

determining a length of the fetched load data for all of the plurality of addresses is less than a length of the vector register; and

iteratively setting one or more residue bytes in the vector register to a pad value, wherein each iteration of setting the one or more residue bytes comprises:

setting a first residue byte of the one or more residue bytes to the pad value according to big endian byte-ordering or little endian byte-ordering; and

proceeding to a next residue byte of the one or more residue bytes.

12. The system of claim 11 , wherein data is loaded in leftmost bytes responsive to a determined first byte-ordering, and data is loaded in rightmost bytes responsive to a determined second byte ordering.

13. The system of claim 11 , wherein the pad value is zero.

14. The system of claim 11 , wherein loading data from memory into the vector register further comprises:

retrieving data from memory, wherein the data retrieved is determined by the memory address and the length; and

storing the retrieved data in the vector register based on the determined byte-ordering.