Methods, articles and devices for pulse adjustments to program a memory cell

1. A method of operating a memory device, comprising:

applying one or more programming electrical pulses to one or more memory cells;

detecting one or more parameters related to a programmed state of the one or more memory cells; and

adjusting one or more aspects of one or more subsequent programming electrical pulses based at least in part on a distribution of the one or more detected parameters.

2. The method of claim 1 , wherein the one or more aspects of the one or more subsequent programming electrical pulses comprises one or more of a fall time, a pulse width, or a pulse shape.

3. The method of claim 1 , wherein the one or more parameters comprise:

a resistance value related to at least one of the one or more memory cells, a current flow value related to at least one of the one or more memory cells, a programming value related to at least one of the one or more memory cells, a programming state related to at least one of the one or more memory cells, a programming level related to at least one of the one or more memory cells, or some combination.

4. The method of claim 1 , wherein detecting the one or more parameters comprises:

applying one or more read voltage signals to the one or more memory cells and detecting one or more currents flowing through the one or more memory cells.

5. The method of claim 1 , further comprising:

applying one or more initial programming electrical pulses to the one or more memory cells; and

determining an initial distribution of parameters associated with the one or more memory cells based at least in part on the applied one or more initial programming electrical pulses.

6. The method of claim 5 , wherein determining the initial distribution of parameters associated with the one or more memory cells comprises:

determining a plurality of resistance values associated with individual memory cells of the one or more memory cells.

7. The method of claim 5 , wherein applying the one or more initial programming electrical pulses to the one or more memory cells comprises:

applying a plurality of discrete programming electrical pulses of varying amplitudes to at least one of the one or more memory cells.

8. The method of claim 1 , further comprising:

determining whether the one or more detected parameters each comprise a value less than a range of parameter values associated with memory cells in a reset state.

9. The method of claim 1 , wherein detecting the one or more parameters and adjusting the one or more aspects of the one or more subsequent programming electrical pulses are performed on a periodic basis.

10. The method of claim 1 , wherein detecting the one or more parameters and adjusting the one or more aspects of the one or more subsequent programming electrical pulses are initiated at least in part by a user.

11. An electronic memory apparatus, comprising:

a memory array including a plurality of memory cells; and

a control unit in electronic communication with the memory array, wherein the control unit is operable to:

detect one or more parameter values related to one or more of the memory cells, and

adjust one or more aspects of a programming electrical pulse based at least in part on the one or more detected parameter values, the one or more aspects of the programming electrical pulse comprising one or more of a fall time, a pulse width, or a pulse shape of the programming electrical pulse.

12. The apparatus of claim 11 , wherein the control unit is further operable to apply a plurality of programming electrical pulses having different characteristics to the one or more memory cells.

13. The apparatus of claim 11 , wherein the control unit is further operable to measure one or more currents related to individual memory cells of the one or more memory cells to detect one or more resistance values.

14. The apparatus of claim 11 , wherein the control unit is further operable to initiate a programming electrical pulse adjustment operation based at least in part on a pre-selected number of memory access cycles.

15. The apparatus of claim 11 , wherein the control unit is further operable to initiate a programming electrical pulse adjustment operation based at least in part in response to a detection of one or more memory cell errors.

16. A method of operating a memory device, comprising:

periodically determining differences between a first set of parameter values associated with an array of memory cells and a second set of parameter values associated with the array of memory cells; and

periodically adjusting one or more aspects of one or more programming electrical pulses based at least in part on the periodically determined differences.

17. The method of claim 16 , wherein the first set of parameter values comprises a first distribution of resistance values associated with the array of memory cells, and the second set of parameter values comprises a second distribution of resistance values associated with the array of memory cells.

18. The method of claim 16 , further comprising:

periodically verifying the one or more periodically adjusted programming electrical pulses at least in part by applying one or more adjusted programming electrical pulses to one or more memory cells of the array of memory cells and by detecting one or more parameter values related to the one or more memory cells based at least in part on the applied one or more adjusted programming electrical pulses.

19. The method of claim 16 , wherein periodically adjusting the one or more aspects of the one or more programming electrical pulses comprises:

adjusting, a control unit of the memory device, the one or more programming electrical pulses based at least in part on a received value indicative of a specified slope of a falling edge of a programming electrical pulse.

20. The method of claim 16 , wherein periodically determining the differences between the first set of parameter values associated with the array of memory cells and the second set of parameter values associated with the array of memory cells comprises:

applying a plurality of read voltage signal pulses to one or more memory cells of the array of memory cells; and

detecting a plurality of current values of current flowing through individual memory cells of the one or more memory cells.