Vertical memory blocks and related devices and methods
Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a dielectric stack of alternating dielectric materials and at least one conductive via extending through the dielectric stack. Semiconductor devices including a vertical memory block include at least one vertical memory block, which includes slots extending between adjacent memory cells of a three-dimensional array. The slots are separated by a first distance in a first portion of the block, and by a second, greater distance in a second portion of the block. Methods of forming vertical memory blocks include forming slots separated by a first distance in a memory array region and by a second, greater distance in a via region. At least one conductive via is formed through a stack of alternating first and second dielectric materials in the via region.
1. A vertical memory block of a semiconductor device, the vertical memory block comprising:
a memory cell region including an array of memory cell pillars extending vertically through the vertical memory block;
at least one stair step region;
at least one via region at least partially located between the memory cell region and the at least one stair step region, the at least one via region including a dielectric stack of alternating dielectric materials and at least one conductive via extending through the dielectric stack; and
a dielectric material within slots extending through the vertical memory block, the slots separated by a first distance in the memory cell region and by a second, greater distance in each of the at least one stair step region and the at least one via region.
2. The vertical memory block of claim 1 , wherein the dielectric stack of alternating dielectric materials comprises a stack of at least sixteen first dielectric materials alternating with at least sixteen second dielectric materials.
3. The vertical memory block of claim 1 , wherein the at least one conductive via is operatively connected to sub-array circuitry.
4. The vertical memory block of claim 3 , wherein the sub-array circuitry comprises a driver circuit.
5. The vertical memory block of claim 1 , wherein the at least one conductive via comprises conductive vias extending through the dielectric stack.
6. The vertical memory block of claim 1 , wherein at least some of the slots extend through the vertical memory block in an interlocking-J pattern.
7. The vertical memory block of claim 1 , further comprising conductive access lines along the slots and respectively coupled to the memory cell pillars of the array.
8. The vertical memory block of claim 7 , wherein overlapping conductive access lines are separated from each other by one dielectric material of the alternating dielectric materials.
9. The vertical memory block of claim 7 , wherein the at least one stair step region comprises contact regions of the conductive access lines.
10. The vertical memory block of claim 9 , further comprising:
at least one additional slot in the at least one stair step region that does not intersect with any other slot of the slots; and
a connection region between the at least one additional slot and the another one of the slots electrically connecting four fingers of a single conductive access line.
11. The vertical memory block of claim 1 , wherein the second, greater distance between the slots in each of the at least one stair step region and the at least one via region is about twice the distance of the first distance between the slots in the memory cell region.
12. The vertical memory block of claim 1 , wherein:
the at least one stair step region comprises two stair step regions at opposing longitudinal ends of the vertical memory block;
the at least one via region comprises two via regions, each of the two via regions being at least partially located longitudinally between a centrally located memory cell region and a respective stair step region; and
each of the two stair step regions comprises at least one stair step structure located remote from the memory cell region.
13. A semiconductor device comprising:
at least one driver circuit on or in a substrate; and
at least one vertical memory block having a longitudinal length and a lateral width, the at least one vertical memory block on the substrate and operatively coupled to the at least one driver circuit, the at least one vertical memory block comprising:
a three-dimensional array of memory cells;
at least one stair step region;
at least one via region at least partially located between the three-dimensional array of memory cells and the at least one stair step region along the longitudinal length of the at least one vertical memory block;
slots extending vertically through the at least one vertical memory block laterally between adjacent memory cells of the three-dimensional array; and
conductive access lines respectively coupled to the three-dimensional array of memory cells, the conductive access lines extending along and adjacent to the slots,
wherein the slots are separated from each other by a first lateral distance in the at least one vertical memory block along the three-dimensional array of memory cells and by a second, greater lateral distance in each of the at least one stair step region and the at least one via region of the at least one vertical memory block adjacent to the three-dimensional array of memory cells.
14. The semiconductor device of claim 13 , further comprising a dielectric stack of alternating dielectric materials in the at least one via region of the at least one vertical memory block and between the slots separated by the second, greater lateral distance.
15. The semiconductor device of claim 14 , further comprising at least one conductive via extending vertically through the dielectric stack of alternating dielectric materials.
16. The semiconductor device of claim 13 , wherein the at least one driver circuit is positioned under the at least one vertical memory block.
17. The semiconductor device of claim 13 , wherein the slots are filled with a dielectric material.
18. The semiconductor device of claim 13 , wherein the dielectric material filling the slots comprises an oxide material.
19. The semiconductor device of claim 13 , wherein the memory cells comprise metal-oxide-nitride-oxide-semiconductor (MONOS) type memory cells.
20. The semiconductor device of claim 13 , wherein the memory cells comprise central pillars of a semiconductor material at least partially surrounded by a charge trapping material.
21. The semiconductor device of claim 13 , wherein at least some of the slots diverge from each other from the first lateral distance to the second, greater lateral distance at an acute angle.
22. A method of forming a vertical memory block of a semiconductor device, the method comprising:
forming a stack of alternating first dielectric materials and second dielectric materials;
removing portions of the first dielectric materials and second dielectric materials to form slots extending through the stack, the slots separated by a first distance in a memory array region of the vertical memory block and separated by a second, greater distance in each of a stair step region and a via region of the vertical memory block, the via region being at least partially located between the memory array region and the stair step region;
removing portions of the second dielectric materials adjacent to the slots to form access line gaps extending along the slots;
forming a conductive material within the access line gaps to form conductive access lines; and
forming at least one conductive via extending through the first dielectric materials and the second dielectric materials in the via region.
23. The method of claim 22 , further comprising forming memory cell pillars through the stack of alternating first dielectric materials and second dielectric materials, wherein forming a conductive material within the access line gaps comprises coupling the memory cell pillars to the conductive access lines.
24. The method of claim 22 , further comprising:
forming a stair step structure in the stair step region proximate a longitudinal end of the vertical memory block, the stair step structure defining contact regions of the conductive access lines; and
forming conductive word line contacts to electrically connect to the contact regions defined by the stair step structure.
25. The method of claim 24 , further comprising forming an additional slot in the stair step region of the vertical memory block, the additional slot terminating at about the first distance or less from one of the other slots to leave a connection region between the additional slot and the one of the other slots, wherein forming the stair step structure comprises forming four stair step structures physically and electrically connected to each other through the connection region.