IP Library Granted Patent US 9,996,297
Granted Patent B2
US 9,996,297 · App. 14/942,726 · Granted Jun 12, 2018

Hot-cold data separation method in flash translation layer

Inventor: Fan Zhang (Fremont, CA)
Assignee: SK Hynix Inc.
G06F3/064G06F3/0608G06F3/0616G06F3/0647G06F3/0679G06F12/0246G06F2212/1036G06F2212/7205
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Quick Facts
Patent No.
US 9,996,297
App. No.
14/942,726
Granted
Jun 12, 2018
Kind
B2
Abstract

A method of data separation includes receiving a host write command operation, identifying temperature of data contained in memory blocks during the host write command operation, selecting a victim block of the memory blocks based on the identified temperature, moving data from the victim block to a destination block, and assigning a sequence number to the destination block when the destination block is full.

Claims (42)

1. A method of data separation, comprising:

receiving a host write command operation;

identifying temperature of data contained in memory blocks of a memory device during the host write command operation, clustering the memory blocks of similar identified temperature, and assigning a predetermined number of blocks for each temperature cluster;

selecting a victim block based on at least the identified temperature from the temperature clusters, wherein

when each number of blocks of every temperature cluster is less than or equal to the respective assigned predetermined number of blocks, the victim block is selected from all the memory blocks on the memory device, and

when the number of blocks of any one of the temperature clusters is greater than the assigned predetermined number of blocks of the respective temperature cluster, the victim block is selected from memory blocks of the respective temperature cluster;

moving data from the victim block to a destination block; and

assigning a sequence number to the destination block when the destination block is full.

2. The method of claim 1 , wherein the victim block is selected as the block with the least number of valid pages from the clustered memory blocks.

3. The method of claim 1 , further comprising wear leveling during the host write command operation.

4. The method of claim 3 , further comprising performing garbage collection after the wear leveling.

5. The method of claim 1 , wherein the identifying step further includes determining temperature of data based on the distance between the assigned sequence number and a current sequence number.

6. A system for data separation, comprising:

a temperature determiner suitable for identifying temperature of data contained in memory blocks during a host write command; and

a controller suitable for:

receiving a host write command operation;

identifying temperature of data contained in memory blocks of a memory device during the host write command operation, clustering the memory blocks of similar identified temperature, and assigning a predetermined number of blocks for each temperature cluster;

selecting a victim block based on at least the identified temperature from the temperature clusters, wherein

when each number of blocks of every temperature cluster is less than or equal to the respective assigned predetermined number of blocks, the victim block is selected from all the memory blocks on the memory device, and

when the number of blocks of any one of the temperature clusters is greater than the assigned predetermined number of blocks of the respective temperature cluster, the victim block is selected from memory blocks of the respective temperature cluster;

moving data from the victim block to a destination block; and

assigning a sequence number to the destination block when the destination block is full.

7. The system of claim 6 , wherein the victim block is selected as the block with the least number of valid pages from the clustered memory blocks.

8. The system of claim 6 , wherein the controller is further suitable for wearing level during the host write command operation.

9. The system of claim 8 , wherein the controller is further suitable for performing garbage collection after the wear leveling.

10. The system of claim 6 , wherein the temperature determiner is further suitable for determining temperature of data based on the distance between the assigned sequence number and a current sequence number.

11. A memory system comprising:

a processor; and

a non-transitory computer readable storage medium coupled to the processor, embedding computer program products executed by the processor, including computer instructions configured to:

receive a host write command operation;

identify temperature of data contained in memory blocks of a memory device during the host write command operation, cluster memory blocks of similar identified temperature, and assign a predetermined number of blocks for each temperature cluster;

select a victim block based on at least the identified temperature from the temperature clusters, wherein

when each number of blocks of every temperature cluster is less than or equal to the respective assigned predetermined number of blocks, the victim block is selected from all the memory blocks on the memory device, and

when the number of blocks of any one of the temperature clusters is greater than the assigned predetermined number of blocks of the respective temperature cluster, the victim block is selected from memory blocks of the respective temperature cluster;

move data from the victim block to a destination block; and

assign a sequence number to the destination block when the destination block is full.

12. The memory system of claim 11 , wherein the computer instructions are further configured to select the victim block as the block with the least number of valid pages from the clustered memory blocks.

13. The memory system of claim 11 , wherein the computer instructions are further configured to

wear level during the host write command operation.

14. The memory system of claim 11 , wherein the computer instructions are further configured to determine temperature of data based on the distance between the assigned sequence number and a current sequence number.

15. The memory system of claim 11 , wherein the computer instructions are further configured to

perform garbage collection after the wear leveling.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2017
From: SK HYNIX MEMORY SOLUTIONS INC.
To: SK HYNIX INC.
Reel/Frame 044899/0443 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2015
From: ZHANG, FAN
To: SK HYNIX MEMORY SOLUTIONS INC.
Reel/Frame 037251/0858 →
Continuity (2)
Provisional Application 62079697 · Nov 14, 2014
Related Publication 20160139812A1 · May 19, 2016