Method for preventing delamination and cracks in group III-V wafers
View Patent ↗In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.
1. A method comprising:
growing a III-Nitride body over a group IV substrate in a semiconductor wafer;
forming at least one device layer over said III-Nitride body;
etching grid array trenches in said III-Nitride body;
forming an edge trench around a perimeter of said semiconductor wafer, said edge trench terminating over a top surface of said group IV substrate;
forming separate dies by cutting said semiconductor wafer approximately along said grid array trenches.
2. The method of claim 1 , further comprising etching said grid array trenches in said group IV substrate.
3. The method of claim 1 , wherein said at least one device layer is a metal layer.
4. The method of claim 1 , wherein said at least one device layer is a dielectric layer.
5. The method of claim 1 , wherein said at least one device layer is a semiconductor layer.
6. The method of claim 1 , wherein said group IV substrate is selected from the group consisting of a silicon substrate, a sapphire substrate, a silicon carbide substrate, an SOI substrate, and a SIMOX substrate.
7. A method comprising:
growing a group III-V body over a group IV substrate in a semiconductor wafer;
forming at least one device layer over said group III-V body;
etching trenches in said group III-V body;
forming an edge trench around a perimeter of said semiconductor wafer, said edge trench terminating over a top surface of said group IV substrate;
forming separate dies by cutting said semiconductor wafer approximately along said trenches.
8. The method of claim 7 , further comprising etching said trenches in said group IV substrate.
9. The method of claim 7 , wherein said at least one device layer comprises a metal layer.
10. The method of claim 7 , wherein said at least one device layer comprises a dielectric layer.
11. The method of claim 7 , wherein said at least one device layer is a semiconductor layer.
12. The method of claim 7 , wherein said group IV substrate comprises silicon.
13. The method of claim 7 , wherein said group IV substrate comprises sapphire.
14. The method of claim 7 , wherein said group IV substrate comprises silicon carbide.
15. The method of claim 7 , wherein said group IV substrate comprises an SOI substrate.
16. The method of claim 7 , wherein said group IV substrate comprises a SIMOX substrate.