Integrated assemblies
View Patent ↗Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have majority carriers of the same conductivity type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.
1. An integrated assembly, comprising:
a semiconductor channel material comprising a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region; both the more-heavily-doped region and the less-heavily-doped region having majority carriers of the same conductivity type; and
a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material; the gating region having a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region; the interconnecting region extending laterally outwardly from the gating region on a side opposite the semiconductor channel region, and being narrower than the length of the gating region.
2. The integrated assembly of claim 1 wherein the gating structure and semiconductor channel material are incorporated into a select device electrically coupled in series with a plurality of memory cells.
3. The integrated assembly of claim 2 wherein the memory cells are vertically-stacked over the select device.
4. The integrated assembly of claim 1 wherein said same conductivity type is an n-type.
5. The integrated assembly of claim 1 wherein said same dopant type is a p-type.
6. The integrated assembly of claim 1 wherein the channel material is supported by a semiconductor base having a substantially horizontal primary surface, and wherein the channel material extends primarily substantially orthogonally relative to the substantially horizontal primary surface.
7. The integrated assembly of claim 1 wherein the common and continuous material comprises metal.
8. The integrated assembly of claim 1 wherein the common and continuous material comprises tungsten or tantalum.
9. The integrated assembly of claim 1 wherein the gating structure extends within a stack of alternating first and second insulating materials; a bottom surface of the gating region being along a lower tier of first insulative material; a bottom surface of the interconnecting region being along a higher tier of first insulative material; and an intermediate tier of second insulative material being between the lower and higher tiers of the first insulative material and being adjacent said side of the gating region.
10. An integrated assembly, comprising:
vertically-stacked memory cells over a select device;
first semiconductor channel material along the memory cells;
second semiconductor channel material comprised by the select device; the second semiconductor channel material comprising a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region; both the more-heavily-doped region and the less-heavily-doped region having majority carriers of the same conductivity type; and
a gating structure comprised by the select device, the gating structure being adjacent the second semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material; the gating region having a length extending across a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region; the interconnecting region extending laterally outwardly from the gating region on a side opposite the second semiconductor channel region, and being narrower than the length of the gating region.
11. The integrated assembly of claim 10 wherein the vertically-stacked memory cells are part of a NOT-AND (NAND) memory array.
12. The integrated assembly of claim 10 wherein the interconnecting region of the gating structure is approximately centered relative to the length of the gating region.
13. The integrated assembly of claim 10 wherein the interconnecting region and the gating region are about the same thickness as one another.
14. The integrated assembly of claim 10 wherein the interconnecting region is thicker than the gating region.
15. The integrated assembly of claim 10 wherein a semiconductor material plug is between the first and second semiconductor channel materials.
16. The integrated assembly of claim 10 wherein the gating structure extends within a stack of alternating first and second insulating materials; a bottom surface of the gating region being along a lower tier of first insulative material; a bottom surface of the interconnecting region being along a higher tier of first insulative material; and an intermediate tier of second insulative material being between the lower and higher tiers of the first insulative material.
17. The integrated assembly of claim 16 wherein the first insulative material comprises silicon dioxide, and the second insulative material comprises a high-k oxide.
18. The integrated assembly of claim 10 wherein the common and continuous material comprises metal.
19. The integrated assembly of claim 10 wherein the second semiconductor channel material includes a ridge over an upper surface of the gating region.
20. The integrated assembly of claim 19 wherein a conductive plug is over and adjacent said ridge.