SEMICONDUCTOR MODULES AND METHODS OF FORMING THE SAME
Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device. The electronic modules further include a substrate such as a DBC substrate, which includes an insulating layer between a first metal layer and a second metal layer, and may include multiple layers of DBC substrates stacked over one another. The first metal layer includes a first portion and a second portion isolated from one another by a trench formed through the first metal layer between the two portions. The first and second switching devices are over the first metal layer, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench.
1 . An electronic device, comprising:
an enhancement-mode transistor comprising a first source electrode, a first gate electrode, a first drain electrode, and a first semiconductor layer, wherein the first source and first gate electrodes are on an opposite side of the first semiconductor layer from the first gate electrode; and
a depletion-mode transistor comprising a second source electrode and a second gate electrode, the second source electrode being over a second semiconductor layer; wherein
the enhancement-mode transistor is mounted directly on top of or over the second source electrode, with the first drain electrode in electrical contact with the second source electrode.
2 . The electronic device of claim 1 , wherein the depletion-mode transistor further comprises a second drain electrode, and the second source and drain electrodes are both on a first side of the second semiconductor layer.
3 . The electronic device of claim 2 , wherein the depletion-mode transistor is a lateral device.
4 . The electronic device of claim 3 , wherein the enhancement-mode transistor is a silicon-based transistor.
5 . The electronic device of claim 4 , wherein the depletion-mode transistor is a III-Nitride transistor.
6 . The electronic device of claim 1 , wherein the first source electrode is electrically connected to the second gate electrode.
7 . The electronic device of claim 1 , wherein the depletion-mode transistor comprises an insulator layer on the semiconductor layer, and the second source electrode is on the insulator layer.
8 . The electronic device of claim 7 , the depletion-mode transistor comprising a device active area and a non-active area, wherein a device channel is in the semiconductor layer in the device active area but not in the semiconductor layer in the non-active area, and the insulator layer is over both the device active area and the non-active area.
9 . The electronic device of claim 8 , wherein the enhancement-mode transistor is on the insulating layer and is directly over a portion of the device active area and a portion of the non-active area.
10 . The electronic device of claim 1 , wherein the depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor.
11 . A method of forming an electronic device, the method comprising:
providing an enhancement-mode transistor comprising a first source electrode, a first gate electrode, a first drain electrode, and a first semiconductor layer, wherein the first source and first gate electrodes are on an opposite side of the first semiconductor layer from the first gate electrode;
providing a depletion-mode transistor comprising a second source electrode and a second gate electrode, the second source electrode being over a second semiconductor layer; and
mounting the enhancement-mode transistor directly on top of or over the second source electrode, with the first drain electrode in electrical contact with the second source electrode.
12 . The method of claim 11 , wherein the depletion-mode transistor is a lateral device.
13 . The method of claim 11 , further comprising wire bonding the second gate electrode to the first source electrode.