Bit line precharging circuit, static RAM, electronic device, and static ram bit line precharging method

1. A bit line precharging circuit comprising:

a first switch having one terminal connected to a bit line and having another terminal connected to a first power source;

a second switch having one terminal connected to the bit line and having another terminal connected to a second power source whose voltage value is higher than a voltage value of the first power source; and

a control circuit including a delay element, in response to a column selection signal and a power down signal, configured to bring the second switch into conduction after a delay time by the delay element after bringing the first switch into conduction at the time of precharge of the bit line.

2. A static RAM comprising:

a memory cell array portion; and

a circuit portion other than the memory cell array portion including a portion that decodes an address signal to the memory cell array portion and generates a control signal, wherein

the memory cell array portion includes:

a plurality of word lines;

a plurality of bit line pairs;

a plurality of memory cells provided at intersection parts of the plurality of word lines and the plurality of bit line pairs;

a plurality of column switches provided in correspondence to each of the plurality of bit line pairs; and

a plurality of bit line precharging circuits configured to charge each of the plurality of bit line pairs, and

each of the plurality of bit line precharging circuits includes:

a first switch having one terminal connected to the bit line pair and having another terminal connected to a first power source;

a second switch having one terminal connected to the bit line pair and having another terminal connected to a second power source whose voltage value is higher than a voltage value of the first power source; and

a control circuit including a delay element, in response to a column selection signal and a power down signal, configured to bring the second switch into conduction after a delay time by the delay element after bringing the first switch into conduction at the time of precharge of the bit line.

3. A static RAM comprising:

a memory cell array portion; and

a circuit portion other than the memory cell array portion including a portion that decodes an address signal to the memory cell array portion and generates a control signal, wherein

the memory cell array portion includes:

a plurality of word lines;

a plurality of bit line pairs;

a plurality of memory cells provided at intersection parts of the plurality of word lines and the plurality of bit line pairs;

a plurality of column switches provided in correspondence to each of the plurality of bit line pairs;

a common bit line pair that is connected in common to the plurality of bit line pairs via the plurality of column switches; and

a common bit line precharging circuit configured to charge the common bit line pair, and

the common bit line precharging circuit includes:

a first switch having one terminal connected to a bit line and having another terminal connected to a first power source;

a second switch having one terminal connected to the bit line and having another terminal connected to a second power source whose voltage value is higher than a voltage value of the first power source; and

a control circuit including a delay element, in response to a column selection signal and a power down signal, configured to bring the second switch into conduction after a delay time by the delay element after bringing the first switch into conduction at the time of precharge of the bit line.

4. The static RAM according to claim 3 , further comprising a plurality of bit line precharging circuits configured to connect each of the plurality of bit line pairs to the second power source.

5. The static RAM according to claim 3 , further comprising a plurality of bit line precharging circuits configured to connect each of the plurality of bit line pairs to the second power source.

6. An electronic device comprising:

a static RAM;

a circuit part other than the static RAM;

a first power source that supplies power to a portion other than a memory cell array portion of the static RAM and the circuit part other than the static RAM; and

a power source voltage generation circuit configured to generate power whose voltage value is higher than the voltage value of the first power source from power of the first power source and to supply the power to the memory cell array portion of the static RAM, wherein

the static RAM includes a bit line precharging circuit including:

a first switch that connects a bit line to a the first power source;

a second switch that connects the bit line to a second power source voltage value is higher than voltage value of the first power source; and

a control circuit including a delay element, in response to a column selection signal and a power down signal, configured to bring the second switch into conduction after a delay time by the delay element after bringing the first switch into conduction at the time of precharge of the bit line.

7. A static RAM bit line precharging method comprising the steps of:

charging a bit line, in response to a column selection signal, to a first voltage value by switching a first switch having one terminal connected to a bit line and having another terminal connected to a first power source; and

charging the bit line, in response to a power down signal, to a second voltage value higher than the first voltage value after a first delay time by switching a second switch having one terminal connected to the bit line and having another terminal connected to a second power source whose voltage value is higher than a voltage value of the first power source.

8. A bit line precharging circuit comprising:

a first switch having one terminal connected to a bit line and having another terminal connected to a first power source;

a second switch having one terminal connected to the bit line and having another terminal connected to a second power source whose voltage value is higher than a voltage value of the first power source; and

a control circuit including a delay element, in response to an equalizing signal and a power down signal, and configured to bring the second switch into conduction after a delay time by the delay element after bringing the first switch into conduction at the time of precharge of the bit line.