Semiconductor device with mode designation and substrate bias circuits
To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.
1. A semiconductor integrated circuit device comprising:
a first circuit;
a mode designation circuit that designates an operation speed of the first circuit;
a second circuit connected to the first circuit, the second circuit including a P-type SOTB transistor formed on a first semiconductor region so as to interpose a first insulation film, and an N-type SOTB transistor formed on a second semiconductor region so as to interpose a second insulation film; and
a substrate bias circuit connected to the mode designation circuit and capable of supplying a first substrate bias voltage to the first semiconductor region and a second substrate bias voltage to the second semiconductor region,
wherein the substrate bias circuit supplies the first substrate bias voltage to the first semiconductor region, and the second substrate bias voltage to the second semiconductor region when the mode designation circuit designates a first operation mode to operate the first circuit at a first speed, and the substrate bias circuit does not supply the first and second substrate bias voltages to the first and second semiconductor regions, respectively, when the mode designation circuit designates a second operation mode to operate the first circuit at a second speed higher than the first speed,
wherein the second circuit is a static memory which includes a plurality of memory cells,
wherein each of the plurality of memory cells includes a pair of inverter circuits which is configured by the P-type SOTB transistor and the N-type SOTB transistor,
wherein an input of one inverter circuit is connected to an output of the other inverter circuit, and an input of the other inverter circuit is connected to an output of the one inverter circuit,
wherein an absolute value of a threshold voltage of the P-type SOTB transistor in the pair of inverter circuits is equal to an absolute value of a threshold voltage of the N-type SOTB transistor in the pair of inverter circuits, and
wherein the substrate bias circuit supplies the first and second substrate bias voltages in the first operation mode such that the absolute value of the threshold voltage of the P-type SOTB transistor in the pair of inverter circuits is higher than the absolute value of the threshold voltage of the N-type SOTB transistor in the pair of inverter circuits,
wherein the first circuit includes a P-type MOS transistor and an N-type MOS transistor, and
wherein in the first operation mode, the substrate bias circuit supplies a third substrate bias voltage different from the first and second substrate bias voltages to the P-type MOS transistor, and supplies the second substrate bias voltage to the N-type MOS transistor.