Semiconductor device with single ended main I/O line
Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.
1. An apparatus comprising:
a pair of bit lines coupled to a plurality of memory cells;
a sense amplifier array that comprises:
a sense amplifier circuit coupled to the pair of bit lines;
a pair of differential data lines coupled to the sense amplifier circuit;
a first amplifier circuit coupled to the pair of differential data lines;
a single-ended data line; and
a first transistor coupled between the single-ended data line and one of the pair of differential data lines,
wherein the first transistor is configured to receive a first control signal at a control node thereof, and
wherein the first amplifier circuit is configured to change a voltage level of the single-ended data line responsive to a voltage level of the other of the pair of differential data lines in a read operation and further configured to change voltage levels of the pair of differential data lines responsive to a voltage level of the single-ended data line, responsive, at least in part, to the first control signal in a write operation.
2. The apparatus as claimed in claim 1 , further comprising a power line, and wherein the first amplifier circuit further comprises:
a second transistor coupled between the other of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; and
a third transistor coupled between the single-ended data line and the power line and coupled to the other of the pair of differential data lines at a control node thereof.
3. The apparatus as claimed in claim 2 , wherein the first transistor is greater in thickness of a gate oxide film than each of the second transistor and the third transistor.
4. The apparatus as claimed in claim 2 , wherein the first amplifier circuit further comprises:
a fourth transistor coupled between the second transistor and the power line; and
a fifth transistor coupled between the third transistor and the power line,
wherein the fourth transistor is configured to receive a second control signal at a control node thereof, the fifth transistor is configured to receive a third control signal at a control node thereof, and
wherein each of the first and second control signals are activated during a write operation and the third control signal is activated during a read operation.
5. The apparatus as claimed in claim 2 , wherein the first amplifier circuit further comprises:
a fourth transistor coupled between the second transistor and the power line; and
a fifth transistor coupled between the third transistor and the power line, and
wherein the fourth transistor is configured to receive a second control signal at a control node thereof, the fifth transistor is configured to receive a third control signal at a control node thereof, and
wherein an active level of the first control signal is greater in voltage level than active levels of the second and third control signals.
6. The apparatus as claimed in claim 1 , further comprising a first driver circuit coupled to the pair of differential data lines and configured to respond to a first logic level of the other of the pair of differential data lines to drive the one of the pair of differential data lines to a second logic level.
7. The apparatus as claimed in claim 1 , further comprising a second driver circuit coupled to the pair of differential data lines and configured to respond to a first logic level of the one of the pair of differential data lines to drive the other of the pair of differential data lines to a second logic level.
8. The apparatus as claimed in claim 1 , further comprising a second amplifier circuit coupled to the single-ended data line and including a first input transistor that is coupled to the single-ended data line at a control node thereof and a second input transistor that is configured to receive a reference voltage at a control node thereof.
9. The apparatus as claimed in claim 1 , further comprising a second amplifier circuit coupled to the single-ended data line and including a first input transistor coupled to the single-ended data line at a control node thereof and a second input transistor coupled to the single-ended data line at a control node thereof with an intervention of a pass transistor therebetween.
10. The apparatus of claim 9 , wherein the pass transistor comprises a control node configured to receive a precharge signal.
11. The apparatus of claim 10 , wherein the first input transistor is configured to decrease a drain voltage faster than the second input transistor in a read operation.
12. The apparatus as claimed in claim 9 , wherein the first input transistor is different in at least one of channel width and channel length from the second input transistor.
13. An apparatus comprising:
an amplifier including an input node, a first input transistor coupled to the input node at a control node thereof and a second input transistor coupled to the input node at a control node thereof with an intervention of a pass transistor therebetween, and wherein the first transistor and the second transistor are equal in conductivity type to each other.
14. The apparatus as claimed in claim 13 , wherein the first input transistor is different in at least one of channel width and channel length from the second input transistor.
15. An apparatus comprising:
a pair of bit lines coupled to a plurality of memory cells;
a sense amplifier circuit coupled to the pair of bit lines;
a pair of differential data lines coupled to the sense amplifier;
a single-ended data line;
a power line;
a first transistor coupled between one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof;
a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and
a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.
16. The apparatus of claim 15 , wherein the second transistor is coupled to a second amplifier circuit via the single-ended data line, and
wherein the second amplifier circuit comprises a first input transistor coupled to the single-ended data line at a control node thereof and a second input transistor coupled to the single-ended data line at a control node thereof with an intervention of a pass transistor therebetween.
17. The apparatus of claim 15 , further comprising:
a fourth transistor coupled between the first transistor and the power line; and
a fifth transistor coupled between the second transistor and the power line, and
the third transistor is configured to receive a first control signal at a control node thereof, the fourth transistor is configured to receive a second control signal at a control node thereof, the fifth transistor is configured to receive a third control signal at a control node thereof, each of the first and second control signals are activated during a write operation and the third control signal is activated during a read operation.
18. The apparatus of claim 17 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are N-channel transistors.
19. The apparatus of claim 17 , wherein an active level of the first control signal is greater in voltage level than active levels of the second and third control signals.
20. The apparatus of claim 18 , wherein the third transistor includes a thicker gate insulating film than each of the first transistor and the second transistor.
21. The apparatus of claim 15 , further comprising a multi-level wiring structure including a lower wiring layer and an upper wiring layer that is located above the first wiring layer, and wherein the pair of differential data lines is formed from the lower wiring layer and the single-ended data line is formed from the lower wiring layer.