IP Library Granted Patent US 10,256,309
Granted Patent B2
US 10,256,309 · App. 14/953,698 · Granted Apr 9, 2019

Memory cells having electrically conductive nanodots

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,256,309
App. No.
14/953,698
Granted
Apr 9, 2019
Kind
B2
Abstract

Memory cells having electrically conductive nanodots between a charge storage material and a control gate are useful in non-volatile memory devices and electronic systems.

Claims (40)

1. A memory cell, comprising:

a first dielectric between a charge storage material and a semiconductor;

a plurality of electrically conductive nanodots between the charge storage material and a control gate; and

a second dielectric between the control gate and the plurality of electrically conductive nanodots;

wherein each electrically conductive nanodot of the plurality of electrically conductive nanodots is

in contact with a particular surface between the charge storage material and the second dielectric; and

wherein a portion of the second dielectric is in contact with the particular surface.

2. The memory cell of claim 1 , wherein the charge storage material comprises an electrically conductive charge storage material.

3. The memory cell of claim 2 , wherein the conductive charge storage material comprises a conductively doped semiconductor material.

4. The memory cell of claim 1 , wherein the charge storage material comprises a silicon-containing material.

5. The memory cell of claim 4 , wherein the silicon-containing material comprises at least one material selected from the group consisting of monocrystalline silicon, amorphous silicon and polycrystalline silicon.

6. The memory cell of claim 1 , further comprising a barrier material between the charge storage material and the plurality of electrically conductive nanodots, wherein the particular surface is a surface of the barrier material.

7. The memory cell of claim 6 , wherein the barrier material is a nitridized material selected from the group consisting of a nitridized product of the charge storage material and a nitridized product of an oxidized product of the charge storage material.

8. The memory cell of claim 6 , wherein a portion of the second dielectric is in contact with the surface of the barrier material.

9. The memory cell of claim 8 , wherein each of the electrically conductive nanodots of the plurality of electrically conductive nanodots is in contact with the surface of the barrier material.

10. The memory cell of claim 1 , wherein each of the electrically conductive nanodots of the plurality of electrically conductive nanodots is in contact with material other than the second dielectric.

11. The memory cell of claim 10 , wherein each of the electrically conductive nanodots of the plurality of electrically conductive nanodots is overlying and in contact with the charge storage material, wherein the particular surface is a surface of the charge storage material.

12. A memory cell, comprising:

a first dielectric between an electrically conductive charge storage material and a semiconductor;

a plurality of metal-containing electrically conductive nanodots between the electrically conductive charge storage material and a control gate;

a dielectric barrier between the plurality of metal-containing electrically conductive nanodots and the electrically conductive charge storage material; and

a second dielectric between the control gate and the metal-containing electrically conductive nanodots;

wherein each metal-containing electrically conductive nanodot of the plurality of metal-containing electrically conductive nanodots is

in contact with a surface of the dielectric barrier; and

wherein a portion of the second dielectric is in contact with the surface of the dielectric barrier.

13. The memory cell of claim 12 , wherein the electrically conductive charge storage material comprises a silicon-containing material selected from the group consisting of conductively doped monocrystalline silicon, conductively doped amorphous silicon and conductively doped polycrystalline silicon.

14. The memory cell of claim 12 , wherein the dielectric barrier comprises a silicon-containing dielectric material selected from the group consisting of a silicon oxide, a silicon nitride and a silicon oxynitride.

15. The memory cell of claim 12 , wherein the electrically conductive charge storage material comprises a silicon-containing material and wherein the dielectric barrier comprises nitridized silicon-containing material of the electrically conductive charge storage material.

16. The memory cell of claim 12 , wherein the plurality of metal-containing electrically conductive nanodots comprise nanodots comprising at least one metal-containing material selected from the group consisting of elemental metals, metal alloys, metal nitrides and metal silicides.

17. The memory cell of claim 16 , wherein the metals of the elemental metals, metal alloys, metal nitrides and metal silicides of the at least one metal-containing material are selected from the group consisting of titanium, tantalum, tungsten, ruthenium, rhodium, and platinum.

18. A memory cell, comprising:

a first dielectric between an electrically conductive silicon-containing charge storage material and a semiconductor;

a plurality of metal-containing electrically conductive nanodots between the electrically conductive silicon-containing charge storage material and a control gate;

a nitridized dielectric barrier between the plurality of metal-containing electrically conductive nanodots and the electrically conductive silicon-containing charge storage material; and

a second dielectric between the control gate and the metal-containing electrically conductive nanodots;

wherein each metal-containing electrically conductive nanodot of the plurality of metal-containing electrically conductive nanodots is

in contact with a surface of the nitridized dielectric barrier; and

wherein a portion of the second dielectric is in contact with the surface of the nitridized dielectric barrier.

19. The memory cell of claim 18 , wherein only a portion of the second dielectric is in contact with the nitridized dielectric barrier.

20. The memory cell of claim 19 , wherein a portion of each of the metal-containing electrically conductive nanodots of the plurality of metal-containing electrically conductive nanodots is in contact with the surface of the nitridized dielectric barrier.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →