Sequential memory operation without deactivating access line signals
Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.
1. An apparatus comprising:
data lines;
an access line;
a first group of memory cells coupled to the access line, each of the data lines coupled to a respective memory cell in the first group of memory cells;
a second group of memory cells coupled to the access line, each of the data lines coupled to a respective memory cell in the second group of memory cells, wherein the first group of memory cells and the second group of memory cells are included in a same block of memory cells, the first group of memory cells includes a first memory cell, the second group of memory cells includes a second memory cell, the first memory cell is included a first memory cell string, the second memory cell is included in a second memory cell string, the first and second memory cell strings share a same data line of the data lines, the first and second groups of memory cells share same control gates, the control gates including a first conductive material located on a first level of the apparatus, and a second conductive material located on a second level of the apparatus;
a module to determine, during a first time interval of a memory operation, values of information stored in the first group of memory cells, to determine, during a second time interval of the memory operation, values of information stored in the second group of memory cells, and to apply a signal having a positive voltage value to the access line during the first and second time intervals and during a time interval between the first and second time intervals.
2. The apparatus of claim 1 , further comprising sense amplifiers, each of the sense amplifiers coupled to a respective data line of the data lines, the sense amplifiers configured to concurrently sense the data lines during the first time interval.
3. The apparatus of claim 2 , wherein the sense amplifiers are configured to concurrently sense the data lines during the second time interval.
4. The apparatus of claim 2 , further comprising latches, each of the latches coupled to a respective sense amplifier of the sense amplifiers, the latches configured to concurrently latch values of information stored in the first group of memory cells sensed by the sense amplifiers.
5. The apparatus of claim 4 , wherein the latches are configured to concurrently latch values of information stored in the second group of memory cells sensed by the sense amplifiers.
6. An apparatus comprising:
data lines;
an access line;
a first group of memory cells coupled to the access line, each of the data lines coupled to a respective memory cell in the first group of memory cells;
a second group of memory cells coupled to the access line, each of the data lines coupled to a respective memory cell in the second group of memory cells;
a module to determine, during a first time interval of a memory operation, values of information stored in the first group of memory cells, to determine, during a second time interval of the memory operation, values of information stored in the second group of memory cells, and to apply a signal having a positive voltage value to the access line during the first and second time intervals and during a time interval between the first and second time intervals;
sense amplifiers, each of the sense amplifiers coupled to a respective data line of the data lines, the sense amplifiers configured to concurrently sense the data lines during the first time interval;
latches, each of the latches coupled to a respective sense amplifier of the sense amplifiers, the latches configured to concurrently latch values of information stored in the first group of memory cells sensed by the sense amplifiers, wherein the latches are configured to concurrently latch values of information stored in the second group of memory cells sensed by the sense amplifiers, and the latches are configured to be set to a state during a time interval after data lines are sensed by the sense amplifiers during the first time interval and before the data lines are sensed by the sense amplifiers during the second time interval.
7. The apparatus of claim 1 , further comprising sense amplifiers, wherein each of the sense amplifiers is configured to not precharge a respective data line of the data lines between the first and second time intervals.
8. The apparatus of claim 7 , wherein the first and second group of memory cells are formed over a substrate and the sense amplifiers are formed between the substrate and the first and second group of memory cells.
9. The apparatus of claim 1 , wherein the first group of memory cells are included in different memory cell strings.
10. The apparatus of claim 9 , wherein the second group of memory cells are included in different memory cell strings.
11. A method comprising:
activating a signal associated with an access line coupled to a first group of memory cells and a second group of memory cells during a memory operation of a device, wherein the first group of memory cells and the second group of memory cells are included in a same block of memory cells, and the first and second groups of memory cells share same control gates, the control gates including a first conductive material located on a first level of the apparatus, and a second conductive material located on a second level of the apparatus;
sensing data lines of the device during a first time interval of the memory operation, each of the data lines coupled to a respective memory cell in the first group of memory cells; and
sensing the data lines during a second time interval of the memory operation, each of the data lines coupled to a respective memory cell in the second group of memory cells, wherein the signal remains activated during a time interval between the first and second time intervals, and the first group of memory cells includes a first memory cell, the second group of memory cells includes a second memory cell, the first memory cell is included a first memory cell string, the second memory cell is included in a second memory cell string, the first and second memory cell strings share a same data line of the data lines.
12. The method of claim 11 , further comprising:
coupling the data lines to a voltage during the first and second time intervals, the voltage having a positive value; and
decoupling the data lines from the voltage during the time interval between the first and second time intervals.
13. The method of claim 11 , further comprising:
determining the values of information stored in the first group of memory cells based on sensed information obtained during the first time interval; and
determining the values of information stored in the second group of memory cells based on sensed information obtained during the second time interval.
14. A method comprising:
activating a signal associated with an access line coupled to a first group of memory cells and a second group of memory cells during a memory operation of a device;
sensing data lines of the device during a first time interval of the memory operation, each of the data lines coupled to a respective memory cell in the first group of memory cells through a select transistor of a first group of select;
sensing the data lines during a second time interval of the memory operation, each of the data lines coupled to a respective memory cell in the second group of memory cells through a select transistor of a second group of select transistors, wherein the second group of select transistors is different from the first group of select transistors, the signal remains activated during a time interval between the first and second time intervals transistor, and the first group of memory cells includes a first memory cell, the second group of memory cells includes a second memory cell, the first memory cell is included a first memory cell string, the second memory cell is included in a second memory cell string, the first and second memory cell strings share a same data line of the data lines;
latching sensed information, using latches, sensed from the data lines during the first time interval;
latching sensed information, using the latches, sensed from the data lines during the second time interval; and
changing states of the latches during the time interval between the first and second time intervals.
15. A method comprising:
activating a signal associated with an access line coupled to a first group of memory cells and a second group of memory cells during a memory operation of a device;
sensing data lines of the device during a first time interval of the memory operation, each of the data lines coupled to a respective memory cell in the first group of memory cells;
sensing the data lines during a second time interval of the memory operation, each of the data lines coupled to a respective memory cell in the second group of memory cells, wherein the signal remains activated during a time interval between the first and second time intervals;
turning on first select transistors during the first time interval, the first select transistors coupled between the data lines and the first group of memory cells;
turning off the first select transistors during the second time interval; and
turning on second select transistors during the second time interval, the second select transistors coupled between the data lines and the second group of memory cells
turning on third select transistors and fourth select transistors during the first and second time intervals and during the time interval between the first and second time intervals.
16. A method comprising:
activating a signal associated with an access line coupled to a first group of memory cells and a second group of memory cells during a memory operation of a device;
sensing data lines of the device during a first time interval of the memory operation, each of the data lines coupled to a respective memory cell in the first group of memory cells through a select transistor of a first group of select transistors; and
sensing the data lines during a second time interval of the memory operation, each of the data lines coupled to a respective memory cell in the second group of memory cells through a select transistor of a second group of select transistors, wherein the second group of select transistors is different from the first group of select transistors, wherein the signal remains activated during a time interval between the first and second time intervals, activating the signal associated with the access line includes causing the access line to be at different levels during the first time interval, and the first group of memory cells includes a first memory cell, the second group of memory cells includes a second memory cell, the first memory cell is included a first memory cell string, the second memory cell is included in a second memory cell string, the first and second memory cell strings share a same data line of the data lines.
17. The method of claim 16 , wherein activating the signal associated with the access line includes causing the access line to be at different levels during the second time interval.
18. A method comprising:
activating a signal associated with an access line coupled to a first group of memory cells and a second group of memory cells during a memory operation of a device;
sensing data lines of the device during a first time interval of the memory operation, each of the data lines coupled to a respective memory cell in the first group of memory cells; and
sensing the data lines during a second time interval of the memory operation, each of the data lines coupled to a respective memory cell in the second group of memory cells through a select transistor of a second group of select transistors, wherein the second group of select transistors is different from the first group of select transistors, wherein the signal remains activated during a time interval between the first and second time intervals, activating the signal associated with the access line includes causing the access line to be activated from a first level to different levels during the first time interval, to be at a second level greater than the first level during the time interval between the first and second time intervals, and to be at different levels during the second time interval, and the first group of memory cells includes a first memory cell, the second group of memory cells includes a second memory cell, the first memory cell is included a first memory cell string, the second memory cell is included in a second memory cell string, the first and second memory cell strings share a same data line of the data lines.