IP Library Granted Patent US 9,773,910
Granted Patent B2
US 9,773,910 · App. 14/954,967 · Granted Sep 26, 2017

Semiconductor structure and manufacturing method thereof

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Quick Facts
Patent No.
US 9,773,910
App. No.
14/954,967
Granted
Sep 26, 2017
Kind
B2
Abstract

A semiconductor structure includes a semiconductor substrate, at least a semiconductor layer formed on the semiconductor substrate, and at least a fin structure formed on the semiconductor layer. The semiconductor substrate includes a first semiconductor material, the semiconductor layer includes the first semiconductor material and a second semiconductor material, and the fin structure includes at least the first semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The semiconductor layer includes a first width, the fin structure includes a second width, and the second width is smaller than the first width.

Claims (13)

1. A semiconductor structure comprising:

a semiconductor substrate comprising a first semiconductor material;

at least a semiconductor layer formed on the semiconductor substrate, the semiconductor layer comprising the first semiconductor material and a second semiconductor material, a lattice constant of the second semiconductor material being different from a lattice constant of the first semiconductor material, and the semiconductor layer comprising a first width;

a dielectric structure formed on the semiconductor substrate, and the dielectric structure comprising a recess formed therein, wherein a bottom corner of the dielectric structure is encompassed by the semiconductor layer, and the first width of the semiconductor layer is larger than a width of the recess; and

at least a fin formed on the semiconductor layer, the fin comprising at least the first semiconductor material, the fin comprising a second width, and the second width of the fin being smaller than the first width of the semiconductor layer.

2. The semiconductor structure according to claim 1 , wherein the lattice constant of the second semiconductor material is larger than the constant of the first semiconductor material.

3. The semiconductor structure according to claim 1 , wherein the fin further comprises the second semiconductor material.

4. The semiconductor structure according to claim 3 , wherein a concentration of the second semiconductor material in the fin is between 20% and 80%.

5. The semiconductor structure according to claim 1 , wherein the semiconductor layer is formed on a bottom of the recess.

6. The semiconductor structure according to claim 5 , wherein a bottom of the semiconductor layer is lower than a surface of the semiconductor substrate, and the bottom of the semiconductor layer is lower than a bottom of the dielectric structure.

7. The semiconductor structure according to claim 1 , wherein the fin is formed in the recess.

8. The semiconductor structure according to claim 7 , wherein a top surface of the fin is higher than a top surface of the dielectric structure.

9. The semiconductor structure according to claim 1 , further comprising a gate layer formed on the fin.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2015
From: CHIU, CHUNG-YI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 037172/0591 →