IP Library Granted Patent US 9,747,960
Granted Patent B2
US 9,747,960 · App. 14/955,520 · Granted Aug 29, 2017

Apparatuses and methods for converting a mask to an index

Inventor: Patrick A. La Fratta (Boise, ID)
Assignee: Micron Technology, Inc.
G11C7/06G11C7/1006
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Quick Facts
Patent No.
US 9,747,960
App. No.
14/955,520
Granted
Aug 29, 2017
Kind
B2
Abstract

The present disclosure includes apparatuses and methods related to converting a mask to an index. An example apparatus comprises an array of memory cells and periphery logic configured to: generate an indicator mask by resetting, in response to a first control signal, a second digit of a mask different from a first digit of the mask that is set; and convert, in response to a second control signal, a digit position in the indicator mask of the first digit that is set to an identifier value as an index.

Claims (41)

1. An apparatus, comprising:

an array of memory cells; and

periphery logic coupled to the array, the periphery logic being configured to generate indices for respective set digits of a mask comprising a plurality of digits, wherein generating the indices comprises:

generating an indicator mask by resetting, in response to a first control signal, a second set digit of the mask different from a first set digit of the mask; and

converting, in response to a second control signal, a digit position of the first set digit in the indicator mask to an identifier value as an index; and

wherein set digits of the mask indicate columns of the array having a particular attribute.

2. The apparatus of claim 1 , further comprising a controller configured to provide the first and the second control signals.

3. The apparatus of claim 1 , further comprising a controller configured to cause sensing circuitry to determine a revised mask as a result of an XOR logical operation between the mask and the indicator mask.

4. The apparatus of claim 3 , wherein the periphery logic is further configured to reset all digits of the revised mask that are less significant than a first set digit of the revised mask.

5. The apparatus of claim 1 , further comprising a controller configured to cause loading of the mask from sensing circuitry coupled to the array to periphery sense amplifiers distinct from the sensing circuitry.

6. The apparatus of claim 1 , wherein the periphery logic configured to convert further comprises the periphery logic configured to:

provide the indicator mask to an encoder;

encode the indicator mask to the identifier value, the identifier value being a quantity expressed in base N where N is an integer greater than 1; and

provide the quantity to a register of a controller coupled to the array.

7. The apparatus of claim 1 , further comprising a controller configured to cause:

loading of a revised mask into a compute component of sensing circuitry associated with a sense line of the array;

loading of the revised mask into a periphery sense amplifier of the periphery logic;

loading of a revised indicator mask into the periphery sense amplifier; and

loading the revised indicator mask from the periphery sense amplifier to an encoder.

8. The apparatus of claim 1 , further comprising a controller and sensing circuitry coupled to the array, the sensing circuitry comprising a plurality of compute components and corresponding sense amplifiers, the controller being configured to control the sensing circuitry to implement logical operations and store results of the logical operations in the sensing circuitry and/or in memory cells of the array.

9. The apparatus of claim 1 , wherein the periphery logic comprises:

a plurality of sense amplifiers coupled to respective pairs of complementary sense lines; and

an encoder.

10. A method, comprising:

determining a digit position of a first set digit in a mask, wherein each digit in the mask indicates a particular attribute of a corresponding column of memory cells;

generating an index for respective set digits in the mask by:

generating an indicator mask by resetting all set digits of the mask other than the first set digit; and

converting the indicator mask to an identifier value as a first index.

11. The method of claim 10 , further comprising determining a revised mask by performing an XOR logical operation between the mask and the indicator mask.

12. The method of claim 10 , wherein determining the digit position of the first set digit comprises loading the mask from an array of memory cells to periphery sense amplifiers distinct from sensing circuitry coupled to columns of the array.

13. The method of claim 12 , further comprising:

determining a first revised mask by performing an XOR logical operation between the mask and the indicator mask using the sensing circuitry;

storing the first revised mask in the sensing circuitry and copying the first revised mask to the periphery sense amplifiers;

determining a digit position of a first set digit in the revised mask;

generating a revised indicator mask by resetting all digits of the revised mask other than the first set digit in the revised mask; and

converting the revised indicator mask to an identifier value as a second index.

14. The method of claim 10 , wherein the digit position corresponds to a column identifier of an array of memory cells.

15. The method of claim 10 , wherein converting the indicator mask to the identifier comprises:

transferring the indicator mask to an encoder;

encoding the indicator mask to the identifier value, the identifier value being a quantity expressed in base N where N is an integer greater than 1; and

transferring the quantity to a register of a controller.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2015
From: LA FRATTA, PATRICK A.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 037179/0078 →
Continuity (2)
Provisional Application 62085942 · Dec 1, 2014
Related Publication 20160155482A1 · Jun 2, 2016