IP Library Granted Patent US 10,162,786
Granted Patent B2
US 10,162,786 · App. 14/956,063 · Granted Dec 25, 2018

Storage node based on PCI express interface

Inventor: Seong Won Shin (San Jose, CA)
Assignee: SK Hynix Inc.
G06F13/4282G06F13/4022G06F13/4081
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Quick Facts
Patent No.
US 10,162,786
App. No.
14/956,063
Granted
Dec 25, 2018
Kind
B2
Abstract

A storage node includes a storage element module. The module includes a first peripheral component interconnect express (PCIe) switch suitable for uplink connection, a second PCIe switch coupled to the first PCIe switch, and at least one connection element coupled to the second PCIe switch, suitable for coupling with at least one storage element. All PCIe end point elements and uplink connection elements are in a PCIe card form factor as defined in PCI Express Card Electromechanical Specification.

Claims (45)

1. A storage node including a storage element module, the storage element module comprising:

a hierarchical peripheral component interconnect express (PCIe) structure suitable for uplink connection, wherein the hierarchical PCIe structure includes at least one first PCIe switch and at least two second PCIe switches, the at least one first PCIe switch is arranged in a different hierarchical level than the at least two second PCIe switches, the at least one first PCIe switch is coupled to each of the at least two second PCIe switches but not to at least one storage element, and the at least two second PCIe switches are not coupled; and

at least one connection element operably coupling the at least two second PCIe switches to the at least one storage element,

wherein one of the at least two second PCIe switches is suitable for coupling with a first group of the at least one storage element; and another of the at least two second PCIe switches is suitable for coupling with a second group of the at least one storage element.

2. The storage node of claim 1 , further comprising:

a PCIe uplink card coupled to the at least one first PCIe switch, suitable for coupling with a server.

3. The storage node of claim 1 , wherein comprising:

a PCIe uplink card coupled to the at least one first PCIe switch, suitable for coupling with a storage server module.

4. The storage node of claim 1 , further comprising:

a micro storage server module in a PCIe card form factor coupled to the at least one first PCIe switch.

5. The storage node of claim 1 , further comprising:

other connection elements suitable for coupling with at least one network interface card (NIC) in a PCIe card form factor.

6. The storage node of claim 1 , further comprising:

other connection elements suitable for coupling with at least one hardware (H/W) accelerator card in a PCIe card form factor.

7. The storage node of claim 1 , wherein the at least two second PCIe switches are further suitable for coupling with at least one network interface card (NIC).

8. The storage node of claim 1 , further comprising:

a plurality of uplink slots for coupling with the at least one first PCIe switch; and

a plurality of PCIe slots for coupling with the at least two second PCIe switches.

9. A storage node including a storage element module, the storage element module comprising:

a hierarchical peripheral component interconnect express (PCIe) structure suitable for uplink connection, wherein the hierarchical PCIe structure includes at least one first PCIe switch and at least two second PCIe switches, the at least one first PCIe switch is arranged in a different hierarchical level than the at least two second PCIe switches, the at least one first PCIe switch is coupled to each of the at least two second PCIe switches but not to at least one storage element, and the at least two second PCIe switches are not coupled;

at least one connection element operably coupling the at least two second PCIe switches to the at least one storage element;

a plurality of uplink slots for coupling with the at least one first PCIe switch; and

a plurality of PCIe slots for coupling with the at least two second PCIe switches,

wherein the plurality of uplink slots and a portion of the plurality of PCIe slots are arranged in a first backplane, and a remaining portion of the plurality of PCIe slots is arranged in a second plane.

10. The storage node of claim 9 , wherein each of the first and second planes comprises a connector suitable for connecting each other.

11. The storage node of claim 8 , further comprising:

a clock selection block suitable for acquiring a reference clock from one of the plurality of uplink slots; and

at least one buffer coupled between the clock selection block and the plurality of PCIe slots, suitable for providing each of the plurality of PCIe slots with the reference clock.

12. The storage node of claim 11 , wherein the clock selection block is further suitable for providing each of the plurality of uplink slots and the at least one first PCIe switch with the reference clock.

13. The storage node of claim 11 , wherein the at least one buffer is further suitable for providing the at least two second PCIe switches with the reference clock.

14. The storage node of claim 11 , further comprising:

a local oscillator suitable for providing the clock selection block with a clock.

15. A storage node including a storage element module, the storage element module comprising:

a hierarchical peripheral component interconnect express (PCIe) structure suitable for uplink connection, wherein the hierarchical PCIe structure includes at least one first PCIe switch and at least two second PCIe switches, the at least one first PCIe switch is arranged in a different hierarchical level than the at least two second PCIe switches, the at least one first PCIe switch is coupled to each of the at least two second PCIe switches but not to at least one storage element, and the at least two second PCIe switches are not coupled;

at least one connection element operably coupling the at least two second PCIe switches to the at least one storage element;

a plurality of uplink slots for coupling with the at least one first PCIe switch; and

a plurality of PCIe slots for coupling with the at least two second PCIe switches,

wherein each of the plurality of uplink slots and the plurality of PCIe slots is hot swappable.

16. The storage node of claim 15 , further comprising:

a switch button suitable for initiating a hot swap operation for one of the plurality of uplink slots and the plurality of PCIe slots; and

a controller suitable for controlling the hot swap operation.

17. The storage node of claim 16 , further comprising:

an indicator suitable for indicating the hot swap operation.

18. The storage node of claim 8 , wherein the plurality of uplink slots and the plurality of PCIe slots are arranged in open compute project (OCP) compliant chassis.

19. The storage node of claim 8 , wherein the plurality of uplink slots and the plurality of PCIe slots are extractable out of an enclosure of the storage element module.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2017
From: SK HYNIX MEMORY SOLUTIONS INC.
To: SK HYNIX INC.
Reel/Frame 044899/0443 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2016
From: SHIN, SEONG WON
To: SK HYNIX MEMORY SOLUTIONS INC.
Reel/Frame 038739/0190 →
Continuity (2)
Provisional Application 62086010 · Dec 1, 2014
Related Publication 20160154765A1 · Jun 2, 2016
Cited By (1)
US 12,223,358