High voltage metal oxide semiconductor field effect transistor integrated into extremely thin semiconductor on insulator process

1. A method of forming a semiconductor device comprising:

forming a first semiconductor device in the a first device region of a semiconductor on insulator (SOI) substrate, wherein the first semiconductor device includes a first source region and a first drain region that is formed in the SOI layer, raised source and drain regions on the first source and drain regions, and a first gate structure on a channel region portion of the SOI layer; and

forming a second semiconductor device in the second device region of the SOI substrate, wherein the second device includes a second source region and a second drain region that is present in a base semiconductor substrate of the SOI substrate, and a second gate structure including a gate dielectric provided by a buried dielectric layer of the SOI substrate and a gate conductor comprised of a same material as the raised source and drain regions.

2. The method of claim 1 , wherein the second source region and the second drain region are formed in the base semiconductor substrate by ion implantation of an n-type or p-type dopant, wherein the ion implantation of the n-type or p-type dopant in the second device region to form the second source region and the second drain region simultaneously forms a back gate structure in the first device region.

3. The method of claim 1 , wherein the first gate structure is formed by a process comprising:

depositing a gate stack of a first gate dielectric layer and a first conductor layer; and

patterning and etching the gate stack so that a remaining portion provides the first gate structure in the first device region.

4. The method of claim 3 further comprising forming a gate sidewall spacer on the sidewall of the first gate structure.

5. The method of claim 1 , wherein the raised source and drain regions are formed using an epitaxial deposition process that simultaneously forms an epitaxial material portion of the gate conductor for the second gate structure.

6. The method of claim 2 further comprising forming a punch through stop region in the first device region of the base semiconductor substrate, wherein the punch through stop region is present underlying the back gate structure.

7. An electrical device comprising:

a semiconductor on insulator (SOI) substrate;

a first semiconductor device in a first device region of the SOI substrate, the first semiconductor device comprising a first source region and a first drain region that is present in the SOI layer of the SOI substrate in the first device region of the SOI substrate, raised source and drain regions on the first source region and the first drain region; and

a second semiconductor device in a second device region of the SOI substrate, the second semiconductor device comprises a second source region and a second drain region present in a base semiconductor layer of the SOI substrate and a second gate structure, wherein a gate dielectric of the second gate structure is provided by a buried dielectric layer of the SOI substrate between the SOI layer and the base semiconductor substrate and a gate conductor of the second gate structure comprises a same material as the raised source region and the raised drain region.

8. The electrical device of claim 7 , wherein the SOI layer has a thickness of 10 nm to less.

9. The electrical device of claim 7 , wherein the buried dielectric layer of the SOI substrate has a thickness ranging from 10 nm to 30 nm.

10. The electrical device of claim 7 , wherein the first semiconductor device includes a first gate structure, wherein the first gate dielectric layer of the first gate structure has a thickness of 1 nm to 5 nm.

11. The electrical device of claim 7 , wherein the first device region is separated from the second device region by a trench isolation region extending through the SOI layer, the buried dielectric layer and extending into the base semiconductor layer of the SOI substrate.

12. The electrical device of claim 11 , wherein a back gate structure is present underlying the first semiconductor device, the back gate structure having a same conductivity type and present at a same depth within the base semiconductor layer as the second source region and the second drain region.

13. The electrical device of claim 11 , wherein an edge of the second source region and the second drain region is aligned with a sidewall of the second gate structure.

14. The electrical device of claim 11 , wherein an edge of the second source region and the second drain region is offset from a sidewall of the second gate structure.

15. An electrical device comprises:

a semiconductor on insulator (SOI) substrate;

a first semiconductor device in a first region of the SOI substrate, the first semiconductor device comprising a first source region and a first drain region that is present in the SOI layer of the SOI substrate in the first region of the SOI substrate, raised source and drain regions on the first source region and the first drain region; and

a second semiconductor device in a second region of the SOI substrate, the second semiconductor device comprises a second source region and a second drain region present in a base semiconductor layer of the SOI substrate and a second gate structure, wherein a gate dielectric of the second gate structure is provided by a buried dielectric layer of the SOI substrate between the SOI layer and the base semiconductor substrate and a gate conductor of the second gate structure comprises a same material as the raised source region and the raised drain region.

16. The electrical device of claim 15 , wherein the SOI layer has a thickness of 10 nm to less.

17. The electrical device of claim 16 , wherein the buried dielectric layer of the SOI substrate has a thickness ranging from 10 nm to 30 nm.

18. The electrical device of claim 16 , wherein the first semiconductor device includes a first gate structure.

19. The electrical device of claim 18 , wherein the first gate dielectric layer of the first gate structure has a thickness of 1 nm to 5 nm.