High performance transaction-based memory systems

1. A memory system comprising:

a master controller including an address mapping decoder, a transaction queue, and a scheduler;

an interface with a host computer; and

a link bus configured to couple with a slave controller,

wherein the address mapping decoder is configured to decode address mapping information of a memory device coupled to the slave controller, and

wherein the scheduler of the master controller is configured to reorder memory transaction requests received from the host computer in the transaction queue using the address mapping information of the memory device.

2. The memory system of claim 1 , wherein the address mapping information includes a channel ID, a rank ID, a bank ID, and a row ID.

3. The memory system of claim 1 , wherein the master controller further includes a flag constructor and the master controller sends a plurality of flags constructed by the flag constructor to the slave controller over the link bus.

4. The memory system of claim 3 , wherein the plurality of flags includes a require activate flag and a require precharge flag.

5. The memory system of claim 4 , wherein the flag constructor is configured to set the require precharge flag to render an activated page of the memory device open when an incoming memory transaction request received from the host computer includes a channel ID, a rank ID, a bank ID and a row ID of a pending memory transaction request in the transaction queue.

6. A memory module comprising:

a slave controller including a decoder, a scheduler, a command queue, and a read return queue; and

a memory device;

wherein the decoder is configured to receive memory transaction requests, generate memory commands based on the memory transaction requests, and place the memory commands in the command queue, and

wherein the decoder is further configured to receive a plurality of flags and reorder the memory commands in the command queue based the plurality of flags.

7. The memory module of claim 6 , wherein the slave controller further includes a refresh handler configured to change and reorder the memory commands in the command queue based on the plurality of flags and handle refresh operation on the memory device based on the changed and reordered memory commands.

8. The memory module of claim 6 , wherein the scheduler is configured to send the memory commands and addresses associated with the memory commands to the memory device based on the memory commands in the command queue.

9. The memory module of claim 6 , further comprising a packetizer and a read return queue, wherein data received from the memory device is placed in the read return queue, and the packetizer is configured to generate packets including the data and send the packets to a master controller over a link bus.

10. The memory module of claim 6 , wherein slave controller further includes a second scheduler configured to send the memory commands and addresses associated with the memory commands to the memory device in an order the memory commands are placed in the command queue.

11. A method comprising:

receiving address mapping information of a memory device from a slave controller over a link bus;

receiving memory transaction requests from a host computer;

placing the memory transaction requests in a transaction queue; and

reordering the memory transaction requests in the transaction queue using the address mapping information of the memory device.

12. The method of claim 11 , wherein the address mapping information includes a channel ID, a rank ID, a bank ID, and a row ID.

13. The method of claim 11 , further comprising constructing a plurality of flags and sending the plurality of flags to the slave controller over the link bus.

14. The method of claim 13 , wherein the plurality of flags includes a require activate flag and a require precharge flag.

15. The method of claim 14 , further comprising setting the require precharge flag to render an activated page of the memory device open when an incoming memory transaction request received from the host computer includes a channel ID, a rank ID, a bank ID and a row ID of a pending memory transaction request in the transaction queue.

16. A method comprising:

sending address mapping information of a memory device to a master controller over a link bus;

receiving memory transaction requests;

decoding the memory transaction requests and generating memory commands based on the decoded memory transaction requests;

placing the memory commands in a command queue;

receiving a plurality of flags; and

reordering the memory commands in the command queue based the plurality of flags.

17. The method of claim 16 , further comprising changing and reordering the memory commands in the command queue based on the plurality of flags and handing refresh operation on the memory device based on the changed and reordered memory commands.

18. The method of claim 16 , further comprising sending the memory commands and addresses associated with the memory commands to the memory device based on the memory commands in the command queue.

19. The method of claim 16 , further comprising placing data received from the memory device in the read return queue, generating packets including the data, and sending the packets to a master controller over a link bus.

20. The method of claim 16 , further comprising sending the memory commands and addresses associated with the memory commands to the memory device in an order the memory commands are placed in the command queue.