IP Library › Granted Patent US 9,847,365
Granted Patent B2
US 9,847,365 · App. 14/960,018 · Granted Dec 19, 2017

Electronic component and method of manufacturing the same

Inventor: Nicolas Hotellier (Jarrie, FR)
Assignee: STMicroelectronics (Crolles 2) SAS
H01L27/14636H01L21/76898H01L27/1464H01L27/14687H01L27/14689H01L31/1892H01L27/14643
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Quick Facts
Patent No.
US 9,847,365
App. No.
14/960,018
Granted
Dec 19, 2017
Kind
B2
Abstract

An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

Claims (43)

1. A method of manufacturing an electronic component comprising the successive steps of:

a) providing a semiconductor layer having a first surface resting on a first insulating layer resting on a substrate and having a second surface coated with a second insulating layer, and providing an insulating portion in the semiconductor layer extending from the first surface to the second surface;

b) etching an opening through the second insulating layer and a central portion of the insulating portion in the semiconductor layer to the first insulating layer and leaving in place an insulating cladding on lateral walls of the opening;

c) forming a laterally-insulated conductive pin filling the opening, the conductive pin being laterally insulated by the insulating cladding;

d) forming, on the second insulating layer, an interconnection structure comprising a conductive layer portion in contact with the conductive pin;

e) removing the substrate;

f) etching a cavity through the first insulating layer to the conductive pin; and

g) forming a contact pad in the cavity.

2. The manufacturing method of claim 1 , wherein the conductive layer portion belongs to the metallization level of the interconnection structure closest to the second surface.

3. The manufacturing method of claim 1 , wherein, at step c) further comprising filling the opening with a conductive material, and chemical-mechanical polishing to the second insulating layer.

4. The manufacturing method of claim 3 , wherein at step c) further comprising depositing a diffusion barrier layer on the lateral walls and bottom of the opening before filling the opening with the conductive material.

5. A manufacturing method, comprising:

forming a photosensitive region in a semiconductor substrate layer having a front surface and a back surface;

forming a region of insulating material extending from the front surface to the back surface;

etching an opening in the region of insulating material extending from the front surface to the back surface, said opening leaving a portion of the insulating material in place at a peripheral sidewall of said opening to insulate the opening from the semiconductor substrate layer;

completely filling the opening with a metal material to form an electrical block; and

forming electrically interconnecting layers over the front surface, said electrically interconnecting layers including a first electrical connection structure electrically connected to the electrical block and a second electrical connection structure electrically connected to the photosensitive region.

6. The method of claim 5 , further comprising forming an insulating layer on the back surface.

7. The method of claim 6 , further comprising:

forming an aperture through the insulating layer to reach the electrical block; and

filling the aperture with an electrically conducting material to form a connection pad.

8. The method of claim 5 , further comprising:

forming a further insulating layer on the front surface;

forming an electrical contact extending through the further insulating layer to make electrical connection to the photosensitive region in the semiconductor substrate layer, said electrical contact made of a metal material different from the metal material forming the electrical block.

9. The method of claim 8 , wherein forming the electrically interconnecting layers over the front surface comprises:

forming the first electrical connection structure over the further insulating layer, said first electrical connection structure comprising: a first metal layer having a bottom surface in direct contact with a top surface of the electrical block and a first metal via extending from a top surface of the first metal layer; and

forming the second electrical connection structure over the further insulating layer, said second electrical connection structure comprising: a second metal layer having a bottom surface in direct contact with a top surface of the electrical block and a second metal via extending from a top surface of the second metal layer.

10. The method of claim 9 , wherein the first and second metal layers are coplanar.

11. A manufacturing method, comprising:

forming a photosensitive region in a semiconductor substrate layer having a front surface and a back surface;

forming a region of insulating material extending from the front surface to the back surface;

depositing a first insulating layer on the front surface;

depositing a second insulating layer on the back surface;

forming an electrical contact extending through the first insulating layer to make electrical connection to the photosensitive region in the semiconductor substrate layer, said electrical contact made of a first conductive material;

etching an opening extending through the first insulating layer and further extending through the region of insulating material to reach at least to said second insulating layer, said opening leaving a portion of the region of insulating material in place at a peripheral sidewall of said opening to insulate the opening from the semiconductor substrate layer;

completely filling the opening with a second conductive material to form an electrical block, wherein the second conductive material is different from the first conductive material;

forming a first interconnect over the first insulating material, said first interconnect comprising: a first metal layer having a bottom surface in direct contact with a top surface of the electrical block and a first metal via extending from a top surface of the first metal layer; and

forming a second interconnect over the first insulating material, said second interconnect comprising: a second metal layer having a bottom surface in direct contact with a top surface of the electrical contact and a second metal via extending from a top surface of the second metal layer.

12. The method of claim 11 , wherein the first conductive material is tungsten and the second conductive material is copper.

13. The method of claim 11 , further comprising:

forming an aperture through the second insulating layer to reach the electrical block; and

filling the aperture with an electrically conducting material to form a connection pad.

14. The method of claim 11 , wherein the first and second metal layers are coplanar.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2015
From: HOTELLIER, NICOLAS
To: STMICROELECTRONICS (CROLLES 2) SAS
Reel/Frame 037216/0993 →
Priority Claims (1)
FR 15 55654 · Jun 19, 2015 · national
Continuity (1)
Related Publication 20160372510A1 · Dec 22, 2016