Low resistance polysilicon strap
View Patent ↗A low resistance polysilicon (poly) structure includes a first poly coupled to a substrate and having a sidewall. A second poly is separated from the sidewall of the first poly and the substrate by a programming oxide. The first poly and the second poly have substantially a same planarized height above the substrate. The first poly extends from a device region to a strap region, and extends substantially parallel to a first length of the second poly. A second length of the second poly extends away from the first poly in the strap region and includes a salicide. A first diffusion region crosses the first poly and the second poly in the device region. A masked width of the first length of the second poly is defined by an etched spacer. A low resistance contact is coupled to the second length of the second poly in the strap region.
1. A low resistance polysilicon (poly) structure comprising:
a first poly coupled to a substrate, the first poly having a sidewall;
a second poly separated from the sidewall of the first poly and the substrate by a programming oxide, the first poly and the second poly having substantially a same planarized height above the substrate, the first poly extending from a device region to a strap region, the first poly extending substantially parallel to a first length of the second poly, a second length of the second poly extending away from the first poly in the strap region and including a salicide, a first diffusion region crossing the first poly and the second poly in the device region, a masked width of the first length of the second poly defined by an etched spacer; and
a low resistance contact coupled to the second length of the second poly in the strap region.
2. The structure of claim 1 wherein the programming oxide is configured to store a state of a non-volatile memory in a high-K metal gate embedded memory process.
3. The structure of claim 1 wherein the first poly forms a select gate of a memory and the second poly forms a control gate of the memory.
4. The structure of claim 1 wherein the programming oxide is a nanocrystal stack.
5. The structure of claim 1 wherein the programming oxide is an Oxide-Nitride-Oxide (ONO) stack.
6. The structure of claim 1 wherein the first diffusion crosses the first poly and the second poly at a substantially orthogonal angle.
7. The structure of claim 1 wherein the second length of the second poly extends to a third poly of an adjacent memory structure.
8. The structure of claim 1 wherein the first diffusion region is N-type.
9. The structure of claim 1 wherein at least a portion of the second length of the second poly has a recessed height less than the planarized height of the first poly and the second poly.
10. The structure of claim 9 wherein a difference between the recessed height and the planarized height is greater than a variation in a chemical mechanical polish process used to planarize the first poly and the second poly.