Gate-all-around nanowire field-effect transistor device
View Patent ↗A gate-all-around (GAA) nanowire field-effect transistor (FET) device includes a semiconductor substrate, a nanowire on the semiconductor substrate, a gate structure surrounding a central portion of the nanowire, a source/drain region on either side of the gate structure, and at least one dislocation plane in the source/drain region.
1. A gate-all-around (GAA) nanowire field-effect transistor (FET) device, comprising:
a semiconductor substrate;
a nanowire on the semiconductor substrate;
a gate structure surrounding a central portion of the nanowire;
one source/drain region on each one of two opposing sides of the gate structure; and
at least one dislocation plane with a shape of conical frustum in each of the source/drain regions.
2. The GAA nanowire FET device according to claim 1 , wherein the gate structure comprises a gate dielectric layer and a metal gate layer on the gate dielectric layer.
3. The GAA nanowire FET device according to claim 1 further comprising a spacer on a sidewall of the gate structure.
4. The GAA nanowire FET device according to claim 1 further comprising an epitaxial stress-inducing material in the source/drain regions.
5. The GAA nanowire FET device according to claim 4 , wherein the epitaxial stress-inducing material comprises SiC, SiP, SiCP, or a combination thereof.
6. The GAA nanowire FET device according to claim 1 , wherein the nanowire is a silicon nanowire.
7. The GAA nanowire FET device according to claim 1 , wherein the GAA nanowire FET is an N-type metal-oxide-semiconductor field effect transistor.
8. The GAA nanowire FET device according to claim 1 , wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate.
9. The GAA nanowire FET device according to claim 1 , wherein the nanowire is disposed between two connection pads.
10. The GAA nanowire FET device according to claim 1 , wherein the substrate comprises an oxide layer and the nanowire suspends above the oxide layer.
11. The GAA nanowire FET device according to claim 1 , further comprising additional dislocation planes in each of the source/drain regions.
12. The GAA nanowire FET device according to claim 11 , wherein the additional dislocation planes have different extending distances.
13. The GAA nanowire FET device according to claim 12 , wherein at least one of the additional dislocation planes spans the entire thickness of the nanowire.
14. The GAA nanowire FET device according to claim 11 , wherein the numbers of the additional dislocation planes in each of the source/drain regions are different.