Semiconductor device and manufacturing method thereof
A manufacturing method of a semiconductor device includes the following steps. A plurality of select gates are formed on a memory region of a semiconductor substrate. Two charge storage structures are formed between two adjacent select gates. A source region is formed in the semiconductor substrate, and the source region is formed between the two adjacent select gates. An insulation block is formed between the two charge storage structures and formed on the source region. A memory gate is formed on the insulation block, and the memory gate is connected to the two charge storage structures.
1. A manufacturing method of a semiconductor device, comprising:
forming a plurality of select gates on a memory region of a semiconductor substrate;
forming two charge storage structures between two adjacent select gates;
forming a source region in the semiconductor substrate, wherein the source region is formed between the two adjacent select gates;
forming an insulation block on the source region, wherein the insulation block is formed between the two charge storage structures; and
forming a memory gate on the insulation block, wherein the memory gate is connected to the two charge storage structures, wherein each of the charge storage structures comprises:
a first oxide layer;
a nitride layer formed on the first oxide layer; and
a second oxide layer formed on the nitride layer, wherein the second oxide layer and the insulation block are formed by an identical oxidation process, and the source region is formed after the step of forming the first oxide layer and the step of forming the nitride layer and formed before the step of forming the second oxide layer.
2. The manufacturing method of claim 1 , further comprising:
forming a dummy gate on a logic region of the semiconductor substrate.
3. The manufacturing method of claim 2 , wherein the dummy gate and the memory gate are formed by a polysilicon layer.
4. The manufacturing method of claim 3 , further comprising:
performing a recessing process on the memory gate; and
forming a self-aligned silicide (salicide) on the memory gate after the recessing process.
5. The manufacturing method of claim 2 , further comprising:
removing the dummy gate on the logic region and replacing the dummy gate by a metal gate, wherein the method of removing the dummy gate on the logic region and replacing the dummy gate by the metal gate comprises a replacement metal gate (RMG) process.
6. The manufacturing method of claim 5 , further comprising:
forming a high-k dielectric layer on the memory region and the logic region of the semiconductor substrate; and
forming a barrier layer on the high-k dielectric layer, wherein a part of the high-k dielectric layer and a part of the barrier layer are located between the two adjacent select gates.
7. The manufacturing method of claim 6 , wherein the high-k dielectric layer is formed before the step of removing the dummy gate.
8. The manufacturing method of claim 6 , wherein the high-k dielectric layer and the barrier layer are formed after the step of removing the dummy gate.
9. The manufacturing method of claim 6 , wherein at least a part of the high-k dielectric layer and at least a part of the barrier layer are located between the memory gate and the charge storage structure.
10. The manufacturing method of claim 5 , wherein the memory gate and the metal gate on the logic region are formed by the RMG process, and the memory gate comprises a metal conductive material.
11. The manufacturing method of claim 5 , wherein the select gate and the metal gate on the logic region are formed by the RMG process, and the select gate comprises a metal conductive material.