Integrated circuit and storage device including the same

1. An integrated circuit comprising:

an input/output pad;

a driver circuit connected to the input/output pad, the driver circuit being configured to output an output signal to an external device through the input/output pad;

a receiver circuit connected to the input/output pad, the receiver circuit being configured to receive an input signal from the external device through the input/output pad; and

a code generator configured to generate a termination code of the external device in response to a signal output from the receiver circuit.

2. The integrated circuit as set forth in claim 1 , wherein

the code generator is configured to detect a detected duty ratio of the signal output from the receiver circuit.

3. The integrated circuit as set forth in claim 2 , wherein

the termination code includes information on whether the detected duty ratio is greater than a reference ratio or smaller than the reference ratio.

4. The integrated circuit as set forth in claim 1 , wherein

the code generator is configured to detect a high level and a low level of the signal output from the receiver circuit.

5. The integrated circuit as set forth in claim 4 , wherein

the termination code includes information on a magnitude of the high level of the signal output from the receiver circuit and a magnitude of the low level of the signal output from the receiver circuit.

6. The integrated circuit as set forth in claim 1 , wherein

the driver circuit is configured to output the termination code to the external device through the input/output pad as the output signal.

7. The integrated circuit as set forth in claim 1 , further comprising:

a second input/output pad;

a second driver circuit connected to the second input/output pad, the second driver circuit being configured to output a second output signal to a second external device through the second input/output pad; and

a second receiver circuit connected to the second input/output pad, the second receiver circuit being configured to receive a second input signal from the second external device through the second input/output pad.

8. The integrated circuit as set forth in claim 7 , wherein

the second driver circuit is configured to output the termination code to the second external device through the second input/output pad as the second output signal.

9. The integrated circuit as set forth in claim 7 , wherein

the code generator is configured to detect the termination code in response to a command received from the second external device through the second input/output pad as the second input signal.

10. The integrated circuit as set forth in claim 7 , wherein

the code generator is configured to detect the termination code in a test mode.

11. The integrated circuit as set forth in claim 7 , wherein the integrated circuit is configured to transfer a signal output from the receiver circuit to the second driver circuit after retiming the signal output from the receiver circuit and to transfer a signal output from the second receiver circuit to the driver circuit after retiming the signal output from the second receiver circuit.

12. An integrated circuit comprising:

an input/output pad;

a driver circuit connected to the input/output pad, the driver circuit being configured to output an output signal to an external device through the input/output pad, the driver circuit being configured to adjust pull-up drive strength and pull-down drive strength based on a termination code received through the input/output pad; and

a receiver circuit connected to the input/output pad, the receiver circuit being configured to receive an input signal from the external device through the input/output pad.

13. The integrated circuit as set forth in claim 12 , wherein

the driver circuit includes a pull-up driver coupled between the input/output pad and a power supply node,

the power supply node is configured to receive a power supply voltage applied thereto,

the driver circuit includes a pull-down driver coupled between the input/output pad and a ground node,

the ground node is configured to receive a ground voltage applied thereto, and

the driver circuit is configured to adjust the pull-up drive strength of the pull-up driver and the pull-down drive strength of the pull-down driver according to the termination code.

14. The integrated circuit as set forth in claim 13 , wherein

the pull-up driver includes a plurality of switches connected to the power supply node, the pull-up driver includes a plurality of transistors coupled between the switches and the input/output pad, respectively, and

the pull-up driver is configured to apply a voltage equivalently to gates of the transistors according to information output as the output signal, and

the pull-up driver is configured to activate a number of the switches according to the termination code.

15. The integrated circuit as set forth in claim 13 , wherein

the driver circuit is configured to activate one of the pull-up driver and the pull-down driver and to deactivate an other one of the pull-up driver and the pull-down driver when the driver circuit outputs the output signal, and

the driver circuit is configured to simultaneously activate the pull-up drivers and the pull-down drivers when the receiver circuit receives the input signal.

16. An integrated circuit comprising:

a first circuit (IC 1 ) and a second circuit (IC 2 ) configured to communicate with each other using a first communication structure of the IC 1 and a second communication structure of the IC 2 ,

the IC 1 including a first core circuit and a first transceiver circuit,

the IC 2 including a second transceiver circuit,

the IC 2 being configured to transfer a signal to the IC 1 ,

the IC 1 being configured generate a code from the signal and to transfer the code to the IC 2 using the first core circuit, the first transceiver circuit, and the first and second communication structures, and

the second transceiver circuit being configured to adjust a drive strength according to the code transferred from the IC 1 to the IC 2 .

17. The integrated circuit as set forth in claim 16 ,

the first communication structure is a first input/output pad,

the second communication structure is a second input/output pad,

the first transceiver circuit includes a first pull-up resistor circuit and a first pull-down resistor circuit that are connected to the first input/output pad,

the IC 1 is configured to perform a ZQ calibration function on the first transceiver circuit to adjust resistances of the first pull-up resistor circuit and the first pull-down resistor circuit using temperature information sensed from the first transceiver circuit,

the IC 2 is not configured to perform the ZQ calibration function on the second transceiver circuit, and

the second transceiver circuit is configured to adjust pull-up drive strength and pull-down drive strength according to the code transferred from the IC 1 to the IC 2 .

18. The integrated circuit as set forth in claim 16 , wherein the first core circuit is configured to detect a duty ratio of the signal transferred from the IC 2 to the IC 1 .

19. The integrated circuit as set forth in claim 16 , wherein the first core circuit is configured to detect a high level and low level of the signal transferred from the IC 2 to the IC 1 .

20. The integrated circuit as set forth in claim 16 , wherein

the IC 2 includes a memory cell array,

the memory cell array includes a plurality of memory cell strings, and

each of the memory cell strings includes a plurality of memory cells stacked on top of each other in a vertical direction between a ground selection transistor and a string selection transistor.