Semiconductor memory device
View Patent ↗A semiconductor memory device according to an embodiment includes: an insulating layer; a conductive layer stacked above the insulating layer in a first direction, the conductive layer having a second direction as a longitudinal direction and a third direction as a short direction; and a channel semiconductor layer extending in the first direction, and the conductive layer including a recessed portion narrowed in the third direction.
1. A semiconductor memory device comprising:
an insulating layer;
a plurality of conductive layers arranged above the insulating layer in a first direction, the conductive layers being arranged side by side in a third direction with a groove extending in a second direction interposed therebetween, the third direction intersecting with the second direction, each of the conductive layers having the second direction as a longitudinal direction and the third direction as a short direction, the conductive layers including a first conductive layer defined by first opposed grooves, at least one of the first opposed grooves including a first protruding portion extending in the third direction partially through the first conductive layer with a first remaining portion of the first conductor layer remaining between the first opposed grooves at said first protruding portion, a width of the first remaining portion in the third direction being shorter than half of a width in the third direction of the first conductive layer adjacent, in the second direction, the first protruding portion;
a channel semiconductor layer extending in the first direction; and
a conductive wire arranged above the conductive layers in the first direction, the conductive wire extending in the third direction, and being electrically connected to the channel semiconductor layer.
2. The semiconductor memory device according to claim 1 , wherein at least one of said first opposed grooves has a second protruding portion extending in the third direction partially through the first conductive layer with a second remaining portion of the first conductor layer remaining between the first opposed grooves at said second protruding portion, a width of the second remaining portion in the third direction being shorter than half of a width in the third direction of the first conductive layer.
3. The semiconductor memory device according to claim 1 , further comprising:
a contact wire configured to electrically connect the first conductive layer and a wire arranged above the first conductive layer in the first direction, and
a memory area in which the channel semiconductor layer is arranged and a contact area in which the contact wire is arranged, and
the first remaining portion of the first conductive layer being arranged in the contact area.
4. The semiconductor memory device according to claim 2 , wherein said first opposed grooves include plural of said protruding portions arranged in a same pitch in the second direction.
5. The semiconductor memory device according to claim 2 ,
wherein said first opposed grooves include plural of said protruding portions arranged in a plurality of different pitches in the second direction.
6. The semiconductor memory device according to claim 2 , wherein,
said first and second protruding portions extend from the same groove of said first opposed grooves.
7. The semiconductor memory device according to claim 2 , wherein,
said first and second protruding portions extend from respective of said first opposed grooves.
8. The semiconductor memory device according to claim 7 ,
wherein one of the first and second remaining portions is formed between opposed protruding portions extending from both said first opposed grooves.
9. The semiconductor memory device according to claim 1 ,
wherein the conductive layers include a second conductive layer disposed between second opposed grooves adjacent to the first conductive layer in the third direction,
at least one of the second opposed grooves including a second protruding portion extending in the third direction partially through the second conductive layer with a second remaining portion of the second conductor layer remaining between the second opposed grooves at said second protruding portion, a width of the second remaining portion in the third direction being shorter than half of the width of the second conductive layer in the third direction, and
the first remaining portion of the first conductive layer and the second remaining portion of the second conductive layer are arranged in a linearly symmetrical layout aligned in the third direction.
10. The semiconductor memory device according to claim 1 ,
wherein the conductive layers include a second conductive layer disposed between second opposed grooves adjacent to the first conductive layer in the third direction,
at least one of the second opposed grooves including a second protruding portion extending in the third direction partially through the second conductive layer with a second remaining portion of the second conductor layer remaining between the second opposed grooves at said second protruding portion, a width of the second remaining portion in the third direction being shorter than half of the width of the second conductive layer in the third direction, and
the first remaining portion of the first conductive layer and the second remaining portion of the second conductive layer are arranged in a same layout.