Method and structure for flip-chip package reliability monitoring using capacitive sensors groups

1. A method, comprising:

providing a flip-chip package comprising a die bonded to a substrate using a bump between the die and the substrate, and at least one pair of capacitive sensors that measures capacitance between each pair of capacitive sensors over time, said pair of capacitive sensors comprising a first sensor formed on a surface of the die and a second sensor formed opposite the first sensor on a surface of the substrate;

monitoring for and reporting a change in capacitance between each pair of capacitive sensors over time using the at least one pair of capacitive sensors, wherein the change in capacitance is due to a chip-packaging interaction failure; and

creating a sequential inventory of non-critical failures which can be used to create a reliability assessment or diagnostic for the flip-chip package.

2. The method of claim 1 , wherein the chip-packaging interaction failure is crack formation and propagation in flip-chip package underfill, interfill, solder mask, chip, substrate, interposer, or a combination thereof;

delamination of a component of the flip-chip package;

warping of the flip-chip package; or

a combination thereof.

3. The method of claim 1 , wherein the at least one pair of capacitive sensors is a group of capacitor plate pairs or an array of capacitor plate pairs, wherein the group or the array provide spatial localization and propagation information for the failure causing the change in capacitance.

4. The method of claim 1 , wherein the at least one pair of capacitive sensors is located in a position to monitor crack propagation in

chip underfill between a chip and an organic laminate substrate connected through C4 bumps and underfill,

chip interfill between dies connected through C4 bumps and interfill,

chip interfill between a die and an interposer connected through C4 bumps and interfill, or

a combination thereof.

5. The method of claim 1 , wherein the at least one pair of capacitive sensors is located in a position to monitor crack propagation in chip underfill or interfill between a vertical side of the chip and an underfill fillet or interfill fillet.

6. The method of claim 1 , wherein the at least one pair of capacitive sensors is located in a die-corner region, between a die and a substrate, between a die and an interposer, between two dies, or a combination thereof.

7. The method of claim 1 , wherein the at least one pair of capacitive sensors is a component of a monitoring apparatus that can detect and track the initiation and propagation of chip-packaging interaction induced cracking and delamination within the package.

8. The method of claim 7 , wherein the monitoring apparatus comprises the at least one capacitive sensor comprising a pair of capacitor plates electrically connected to an A/D converter which in turn is electrically connected to a microprocessor.

9. The method of claim 8 , wherein the microprocessor calls for a field repair or calls for stress testing upon receiving the electrical signal at the time of the first change in capacitance (SN 1 ).

10. The method of claim 8 , wherein the microprocessor is located in the chip package or external to the chip package.

11. A method, comprising:

providing a flip-chip package comprising a die bonded to a substrate using a bump between the die and the substrate, and at least one pair of capacitive sensors that measures capacitance between each pair of capacitive sensors over time, said pair of capacitive sensors comprising a first sensor formed on a surface of the die and a second sensor formed opposite the first sensor on a surface of the substrate;

monitoring for a change in capacitance between each pair of capacitive sensors over time from time zero to a time of a first change in capacitance, and sending an electrical signal at the time of the first change in capacitance (SN 1 );

monitoring for a change in capacitance from the time of the first change in capacitance to a time of a second change in capacitance, and sending an electrical signal at the time of the second change in capacitance (SN 2 );

continue monitoring and sending an electrical signal at a time of each subsequent change in capacitance (SNx) until final failure of the package, and sending an electrical signal for the final failure (SF);

wherein the electrical signals returning from the at least one pair of capacitive sensors from time zero (S 0 ) to final failure (SF), with intermediate signals (SN 1 , SN 2 , SNx) representing noncritical failures, are S 0 →SN 1 →SN 2 →SNx→SF where S 0 ≠SNx≠SF; and

creating a sequential inventory of non-critical failures which can be used to create a reliability assessment or diagnostic for the flip-chip package;

wherein the change in capacitance over time is due to a chip-packaging interaction failure that is

crack formation and propagation in the flip-chip package underfill, interfill, solder mask, chip, substrate, interposer, or a combination thereof,

delamination of a component of the flip-chip package,

warping of the flip-chip package, or

a combination thereof.