Solid-state imaging device and method for manufacturing solid-state imaging device, and electronic device
A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor well region and is composed of a photoelectric conversion portion and a pixel transistor, an element isolation region provided between the pixels and in the pixels, and an element isolation region being free from an insulation film and being provided between desired pixel transistors.
1. An imaging device, comprising:
a first area including a first set of photodiodes that share a first floating diffusion region and a second set of photodiodes that share a second floating diffusion region, wherein the first set of photodiodes and the second set of photodiodes are arranged along a first direction;
a second area including a first amplification transistor coupled to the first floating diffusion region, a second amplification transistor coupled to the second floating diffusion region, an element isolation region, and a well contact region, wherein the first area and the second area are arranged along a second direction perpendicular to the first direction;
wherein the element isolation region is arranged between the first amplification transistor and the second amplification transistor and comprises an insulating material;
a first reset transistor coupled to the first floating diffusion region; a second reset transistor coupled to the second floating diffusion region; at least one first transfer transistor coupled to the first floating diffusion region; and at least one second transfer transistor coupled to the second floating diffusion region,
wherein the well contact region is arranged between the first amplification transistor and the second amplification transistor along the first direction in the second area,
wherein the imaging device further comprises a third set of photodiodes that share a third floating diffusion region, and
wherein the third set of photodiodes is adjacent to the first set of photodiodes across the second area along the second direction.
2. The imaging device of claim 1 , wherein the insulating material comprises a silicon oxide.
3. The imaging device of claim 2 , wherein the insulating material is disposed as a silicon oxide film.
4. The imaging device of claim 1 , wherein the element isolation region has a shallow trench isolation (STI) structure.
5. The imaging device of claim 1 , wherein the first area further includes an element isolation region that does not include an STI structure.
6. The imaging device of claim 5 , wherein the element isolation region in the first area includes an impurity diffusion region.
7. The imaging device of claim 1 , wherein the well contact region is configured to apply a voltage to a semiconductor well region.
8. The imaging device of claim 1 , wherein the second area further includes a first selection transistor coupled to the first amplification transistor and a second selection transistor coupled to the second amplification transistor.
9. The imaging device of claim 8 , wherein the well contact region is arranged between the first selection transistor and the second selection transistor along the first direction in the second area.
10. The imaging device of claim 1 , further comprising a plurality of first areas arranged alternating with a plurality of second areas along the second direction.
11. The imaging device of claim 1 , wherein each of the first area and the second area extends along the first direction.
12. The imaging device of claim 1 ,
wherein the first set of photodiodes includes a first photodiode and a second photodiode,
wherein the at least one first transfer transistor comprises a first transfer transistor coupled to the first photodiode and the first floating diffusion region, and a second transfer transistor coupled to the second photodiode and the first floating diffusion region,
wherein the second set of photodiodes includes a third photodiode and a fourth photodiode, and
wherein the at least one second transfer transistor comprises a third transfer transistor coupled to the third photodiode and the second floating diffusion region, and a fourth transfer transistor coupled to the fourth photodiode and the second floating diffusion region.
13. The imaging device of claim 1 , wherein the element isolation region is arranged to surround at least the well contact region in a plan view.
14. The imaging device of claim 1 , wherein the element isolation region is arranged to surround at least the first amplification transistor in a plan view.
15. The imaging device of claim 1 , further comprising a plurality of first areas arranged alternating with a plurality of second areas in the second direction,
wherein each of the plurality of first areas and plurality of second areas extends in the first direction, and
wherein the element isolation region has a shallow trench isolation (STI) structure and is arranged to surround at least the first amplification transistor in a plan view.
16. An imaging device comprising:
a first set of photodiodes that share a first floating diffusion region;
a first amplification transistor, a first reset transistor, and at least one first transfer transistor coupled to the first floating diffusion region;
a second set of photodiodes that share a second floating diffusion region, wherein the first set of photodiodes and the second set of photodiodes are arranged along a first direction;
a second amplification transistor, a second reset transistor, and at least one second transfer transistor coupled to the second floating diffusion region;
an element isolation region arranged between the first amplification transistor and the second amplification transistor and comprises an insulating material; and
a well contact region arranged between the first amplification transistor and the second amplification transistor along the first direction,
wherein the first set of photodiodes and the first amplification transistor are arranged along a second direction perpendicular to the first direction,
wherein the imaging device further comprises a third set of photodiodes that share a third floating diffusion region, and
wherein the third set of photodiodes is adjacent to the first set of photodiodes across the first amplification transistor along the second direction.
17. The imaging device of claim 16 , wherein the insulating material comprises a silicon oxide.
18. The imaging device of claim 17 , wherein the insulating material is disposed as a silicon oxide film.
19. The imaging device of claim 16 , wherein the element isolation region has a shallow trench isolation (STI) structure.
20. The imaging device of claim 16 , wherein the well contact region is configured to apply a voltage to a semiconductor well region.
21. The imaging device of claim 16 , further comprising a first selection transistor coupled to the first amplification transistor and a second selection transistor coupled to the second amplification transistor.
22. The imaging device of claim 21 , wherein the well contact region is arranged between the first selection transistor and the second selection transistor along the first direction.
23. The imaging device of claim 16 ,
wherein the first set of photodiodes includes a first photodiode and a second photodiode,
wherein the at least one first transfer transistor comprises a first transfer transistor coupled to the first photodiode and the first floating diffusion region, and a second transfer transistor coupled to the second photodiode and the first floating diffusion region,
wherein the second set of photodiodes includes a third photodiode and a fourth photodiode, and
wherein the at least one second transfer transistor comprises a third transfer transistor coupled to the third photodiode and the second floating diffusion region, and a fourth transfer transistor coupled to the fourth photodiode and the second floating diffusion region.
24. The imaging device of claim 16 , wherein the element isolation region is arranged to surround at least the well contact region in a plan view.
25. The imaging device of claim 16 , wherein the element isolation region is arranged to surround at least the first amplification transistor in a plan view.
26. The imaging device of claim 16 ,
wherein the element isolation region has a shallow trench isolation (STI) structure and is arranged to surround at least the first amplification transistor in a plan view.