Semiconductor device, memory device, and electronic device
View Patent ↗To provide a small, highly reliable memory device with a large storage capacity. A semiconductor device includes a circuit for retaining data and a circuit for reading data. The circuit for retaining data includes a transistor and a capacitor. The circuit for reading data is configured to supply a potential to the circuit for retaining data and read a potential from the circuit for retaining data. The circuit for retaining data and the circuit for reading data are provided in different layers, so that the semiconductor device with a large storage capacity is manufactured.
1. A semiconductor device comprising a first circuit,
the first circuit comprising a first input terminal, a first output terminal, a first transistor, and a second circuit, and
the second circuit comprising a second to a (2n+1)th transistor, a first to an n-th capacitor, a first to an n-th wiring, a first gate wiring, and a first to an n-th storage node (n is an integer of 2 or more),
wherein a gate of the 2i-th transistor is electrically connected to the first gate wiring (i is an integer of 1 to n),
wherein a first terminal of the 2i-th transistor is electrically connected to a gate of the (2i+1)th transistor and a first terminal of the i-th capacitor through the i-th storage node,
wherein the first wiring is electrically connected to a second terminal of the first transistor,
wherein the i-th wiring is electrically connected to a second terminal of the 2i-th transistor,
wherein the first input terminal is electrically connected to a first terminal of the first transistor,
wherein a second terminal of the first transistor is electrically connected to a first terminal of the third transistor,
wherein a second terminal of a (2i−1)th transistor is electrically connected to a first terminal of the (2i+1)th transistor, and
wherein a second terminal of the (2n+1)th transistor is electrically connected to the first output terminal.
2. The semiconductor device according to claim 1 , comprising a memory cell array and a plurality of the first circuits,
wherein the memory cell array comprises a plurality of the second circuits.
3. The semiconductor device according to claim 1 , comprising a plurality of memory cell arrays and a plurality of the first circuits,
wherein the plurality of memory cell arrays each comprises a plurality of the second circuits, and
wherein the plurality of memory cell arrays overlap with each other.
4. The semiconductor device according to claim 1 , comprising a third circuit,
wherein the third circuit is configured to supply a potential to the first circuit and read a potential output from the first circuit,
wherein the first input terminal is electrically connected to the third circuit, and
wherein the first output terminal is electrically connected to the third circuit.
5. The semiconductor device according to claim 4 ,
wherein the second circuit is over the third circuit.
6. The semiconductor device according to claim 1 ,
wherein the first to the (2n+1)th transistor include an oxide semiconductor in a channel formation region.
7. The semiconductor device according to claim 1 ,
wherein the first transistor includes silicon in a channel formation region, and
wherein the second to the (2n+1)th transistor include an oxide semiconductor in a channel formation region.
8. The semiconductor device according to claim 1 ,
wherein at least one of the first to the (2n+1)th transistor includes a back gate.
9. The semiconductor device according to claim 1 ,
wherein the first to the n-th storage node are configured to retain M-bit data (M is an integer of 1 or more) as a potential and output, from the first output terminal, a potential corresponding to the potential maintained at the first to the n-th storage node.
10. A semiconductor device comprising a first circuit,
the first circuit comprising a first input terminal, a first output terminal, a first transistor, and a second circuit, and
the second circuit comprising a second to a (2n+1)th transistor, a first to an n-th capacitor, a first to an n-th wiring, a first gate wiring, and a first to an n-th storage node (n is an integer of 2 or more),
wherein a gate of the 2i-th transistor is electrically connected to the first gate wiring (i is an integer of 1 to n),
wherein a first terminal of the 2i-th transistor is electrically connected to a gate of the (2i+1)th transistor and a first terminal of the i-th capacitor through the i-th storage node,
wherein the first wiring is electrically connected to a second terminal of the first transistor,
wherein the i-th wiring is electrically connected to a second terminal of the 2i-th transistor,
wherein the first input terminal is electrically connected to a first terminal of the third transistor,
wherein a second terminal of a (2i−1)th transistor is electrically connected to a first terminal of the (2i+1)th transistor,
wherein a second terminal of the (2n+1)th transistor is electrically connected to a first terminal of the first transistor, and
wherein a second terminal of the first transistor is electrically connected to the first output terminal.
11. The semiconductor device according to claim 10 , comprising a memory cell array and a plurality of the first circuits,
wherein the memory cell array comprises a plurality of the second circuits.
12. The semiconductor device according to claim 10 , comprising a plurality of memory cell arrays and a plurality of the first circuits,
wherein the plurality of memory cell arrays each comprises a plurality of the second circuits, and
wherein the plurality of memory cell arrays overlap with each other.
13. The semiconductor device according to claim 10 , comprising a third circuit,
wherein the third circuit is configured to supply a potential to the first circuit and read a potential output from the first circuit,
wherein the first input terminal is electrically connected to the third circuit, and
wherein the first output terminal is electrically connected to the third circuit.
14. The semiconductor device according to claim 13 ,
wherein the second circuit is over the third circuit.
15. The semiconductor device according to claim 10 ,
wherein the first to the (2n+1)th transistor include an oxide semiconductor in a channel formation region.
16. The semiconductor device according to claim 10 ,
wherein the first transistor includes silicon in a channel formation region, and
wherein the second to the (2n+1)th transistor include an oxide semiconductor in a channel formation region.
17. The semiconductor device according to claim 10 ,
wherein at least one of the first to the (2n+1)th transistor includes a back gate.
18. The semiconductor device according to claim 10 ,
wherein the first to the n-th storage node are configured to retain M-bit data (M is an integer of 1 or more) as a potential and output, from the first output terminal, a potential corresponding to the potential maintained at the first to the n-th storage node.
19. A semiconductor device comprising:
a first transistor comprising a gate, a first terminal, and a second terminal,
a first memory cell comprising a first capacitor, a second transistor and a third transistor each comprising a gate, a first terminal, and a second terminal;
a second memory cell comprising a second capacitor, a fourth transistor and a fifth transistor each comprising a gate, a first terminal, and a second terminal;
a first wiring and a second wiring; and
a circuit comprising an input terminal and an output terminal,
wherein the first terminal of the second transistor is electrically connected to the first wiring,
wherein the first terminal of the fourth transistor is electrically connected to the second wiring,
wherein the second terminal of the second transistor is electrically connected to a first terminal of the first capacitor,
wherein the second terminal of the fourth transistor is electrically connected to a first terminal of the second capacitor,
wherein the output terminal is electrically connected to the first terminal of the first transistor,
wherein the second terminal of the first transistor is electrically connected to the first terminal of the third transistor,
wherein the second terminal of the third transistor is electrically connected to the first terminal of the fifth transistor, and
wherein the second terminal of the fifth transistor is electrically connected to the input terminal.
20. The semiconductor device according to claim 19 , further comprising:
third to fifth wirings,
wherein the third wiring is electrically connected to the gate of the second transistor and the gate of the fourth transistor,
wherein the fourth wiring is electrically connected to a second terminal of the first capacitor,
wherein the fifth wiring is electrically connected to a second terminal of the second capacitor,
wherein the second terminal of the second transistor is electrically connected to the gate of the third transistor, and
wherein the second terminal of the fourth transistor is electrically connected to the gate of the fifth transistor.
21. The semiconductor device according to claim 19 ,
wherein at least one of the second to fifth transistors includes a back gate.
22. The semiconductor device according to claim 19 ,
wherein the first to fifth transistors include an oxide semiconductor in a channel formation region.