Semiconductor-on-insulator (SOI) device and related methods for making same using non-oxidizing thermal treatment
A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.
1. A semiconductor device comprising:
a semiconductor substrate;
an n-channel metal-oxide semiconductor field-effect transistor (NMOS) including:
a first buried oxide (BOX) layer on said semiconductor substrate,
a first semiconductor layer on said first BOX layer,
a first pair of source and drain regions in the first semiconductor layer, and an n-type channel in the first semiconductor layer between the first pair of source and drain regions, and
a first gate above the n-type channel;
a p-channel metal-oxide semiconductor field-effect transistor (PMOS) including:
a second BOX layer on said semiconductor substrate, the second BOX layer having a thickness that is less than 30 nm,
a second semiconductor layer on said second BOX layer, the second semiconductor layer including silicon germanium and having a thickness that is less than 10 nm, the second semiconductor layer having a germanium concentration of about 27% at a surface of the second semiconductor layer, and a germanium concentration of about 21% at an interface between the second semiconductor layer and the second BOX layer,
a second pair of source and drain regions in the second semiconductor layer, and a p-type channel in the second semiconductor layer between the second pair of source and drain regions, each of the second pair of source and drain regions and the p-type channel including silicon germanium, and
a second gate above the p-type channel; and
a shallow trench isolation (STI) region between said NMOS and said PMOS,
wherein said second BOX layer has a planar upper surface substantially devoid of oxide protrusions adjacent said STI region.
2. The semiconductor device of claim 1 wherein said first semiconductor layer comprises a silicon layer.
3. The semiconductor device of claim 1 wherein the second BOX layer has a substantially uniform thickness.
4. The semiconductor device of claim 1 wherein the first gate comprises a first gate dielectric layer and a first gate electrode layer thereon.
5. The semiconductor device of claim 1 wherein the second gate comprises a second gate dielectric layer and a second gate electrode layer thereon.
6. The semiconductor device of claim 1 further comprising first sidewall spacers adjacent the first gate.
7. The semiconductor device of claim 6 further comprising second sidewall spacers adjacent the second gate.
8. The semiconductor device of claim 7 wherein said first semiconductor layer comprises a silicon layer.
9. A semiconductor device comprising:
a semiconductor substrate;
an n-channel metal-oxide semiconductor field-effect transistor (NMOS) including:
a first buried oxide (BOX) layer on said semiconductor substrate,
a first semiconductor layer on said first BOX layer,
a first source region, a first drain region, and an n-type channel between the first source region and the first drain region, each of the first source region, the first drain region, and the n-type channel positioned in the first semiconductor layer, and
a first gate above the n-type channel;
a p-channel metal-oxide semiconductor field-effect transistor (PMOS) including:
a second BOX layer on said semiconductor substrate,
a second semiconductor layer on said second BOX layer, the second semiconductor layer comprising a layer of silicon germanium having a non-linear diffusion profile of germanium between a surface of the second semiconductor layer and the second BOX layer, the layer of silicon germanium having a germanium concentration of about 27% at the surface of the second semiconductor layer, and a germanium concentration of about 21% at an interface between the second semiconductor layer and the second BOX layer;
a second source region, a second drain region, and a p-type channel between the second source region and the second drain region, each of the second source region, the second drain region, and the p-type channel positioned in the second semiconductor layer and including silicon germanium having the non-linear diffusion profile, and
a second gate above the p-type channel; and
an isolation region between said NMOS and said PMOS,
said second BOX layer having a substantially uniform thickness and a substantially planar upper surface.
10. The semiconductor device of claim 9 wherein said isolation region comprises a shallow trench isolation region.
11. The semiconductor device of claim 9 wherein said first semiconductor layer comprises a silicon layer.
12. The semiconductor device of claim 9 wherein the first gate comprises a first gate dielectric layer and a first gate electrode layer thereon.
13. The semiconductor device of claim 9 wherein the second gate comprises a second gate dielectric layer and a second gate electrode layer thereon.
14. The semiconductor device of claim 9 further comprising first sidewall spacers adjacent the first gate.
15. The semiconductor device of claim 9 further comprising second sidewall spacers adjacent the second gate.
16. A semiconductor device comprising:
a semiconductor substrate;
an n-channel metal-oxide semiconductor field-effect transistor (NMOS) including:
a first buried oxide (BOX) layer on said semiconductor substrate,
a silicon layer on said first BOX layer,
a first pair of source and drain regions in the silicon layer, and an n-type channel in the silicon layer between the first pair of source and drain regions, and
a first gate above the n-type channel;
a p-channel metal-oxide semiconductor field-effect transistor (PMOS) including:
a second BOX layer on said semiconductor substrate, the second BOX layer having a thickness that is less than 30 nm,
a silicon germanium layer on said second BOX layer, the silicon germanium layer having a germanium concentration of about 27% at a surface of the silicon germanium layer and a germanium concentration of about 21% at an interface between the silicon germanium layer and the second BOX layer, the silicon germanium layer having a thickness that is less than 10 nm,
a second pair of source and drain regions in the silicon germanium layer, and a p-type channel in the silicon germanium layer between the second pair of source and drain regions, each of the second pair of source and drain regions, and the p-type channel including silicon germanium, and
a second gate above the p-type channel; and
an isolation region between said NMOS and said PMOS,
said second BOX layer having a thickness adjacent the isolation region that is substantially the same as a thickness in a medial portion thereof.
17. The semiconductor device of claim 16 wherein said isolation region comprises a shallow trench isolation region.
18. The semiconductor device of claim 16 wherein the first gate comprises a first gate dielectric layer and a first gate electrode layer thereon.
19. The semiconductor device of claim 16 wherein the second gate comprises a second gate dielectric layer and a second gate electrode layer thereon.
20. The semiconductor device of claim 16 further comprising first sidewall spacers adjacent the first gate.
21. The semiconductor device of claim 16 further comprising second sidewall spacers adjacent the second gate.