Printed circuit board and method of manufacturing the same
A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes a first circuit layer disposed on an upper surface of a substrate, an insulating layer disposed on the substrate and the first circuit layer, a second circuit layer disposed on an upper surface of the insulating layer, and a via configured to connect between the first circuit layer and the second circuit layer, and a lower part of the via is in contact with the upper surface of the substrate.
1. A printed circuit board comprising:
a first circuit layer on an upper surface of a substrate;
an insulating layer disposed on the substrate and the first circuit layer;
a second circuit layer protrude on an upper surface of the insulating layer; and
a via configured to connect between the first circuit layer and the second circuit layer,
wherein the upper surface of the substrate comprises one portion covered by the first circuit layer and the other portion, wherein a lower part of the via is directly in contact with the other portion of the upper surface of the substrate,
wherein the first circuit layer comprises a circuit pattern, a side surface of the circuit pattern is directly in contact with a side surface of the via, and
wherein the circuit pattern has a smaller line-width than the via, and
the insulating layer is a photosensitive resin layer.
2. The printed circuit board of claim 1 , wherein the second circuit layer comprises an upper via land formed on the upper part of the via.
3. The printed circuit board of claim 1 , wherein the second circuit layer comprises a circuit pattern formed integrally with the via.
4. A printed circuit board comprising:
circuit layers;
an insulating layer disposed between the circuit layers and comprising an insulating resin; and
a via interconnecting the circuit layers and comprising copper,
wherein a lower part of the via comprises a landless via in contact with the insulating layer, one of the circuit layers comprises a circuit pattern having a smaller line-width than the via, and
the insulating layer is a photosensitive resin layer.
5. A printed circuit board comprising:
a lower part circuit layer disposed on a lower surface of an insulating layer;
an upper part circuit layer; and
a via formed in the insulating layer to connect the lower part circuit layer and the upper part circuit layer with each other,
wherein the lower surface of the insulating layer comprises one portion covered by the lower part circuit layer and the other portion,
where the via extends from the lower surface of the upper part circuit layer to the other portion of the lower surface of the insulating layer,
wherein the lower part circuit layer comprises a circuit pattern, a side surface of the circuit pattern is directly in contact with a side surface of the via and
wherein the circuit pattern has a smaller line-width than the via, and
the insulating layer is a photosensitive resin layer.
6. The printed circuit board of claim 5 , wherein the upper part circuit layer comprises an upper via land formed on an upper part of the via.
7. The printed circuit board of claim 5 , wherein the upper part circuit layer comprises a circuit pattern formed integrally with the via.
8. A printed circuit board comprising:
a first circuit layer disposed on one surface of a substrate;
an insulating layer disposed on the substrate and the first circuit layer;
a second circuit layer disposed on the insulating layer; and
a via penetrating the insulating layer and electrically connecting the first circuit layer and the second circuit layer, a portion of a side surface of the via being in contact with the first circuit layer, wherein the one surface of the substrate comprises one portion covered by the first circuit layer and the other portion, wherein a bottom surface of the via is directly in contact with the other portion of the one surface of the substrate, wherein a portion of a side surface of the via is directly in contact with a side surface of the first circuit layer,
and wherein one of the first and second circuit layer comprises a circuit pattern having a smaller line-width than the via, and
the insulating layer is a photosensitive resin layer.