IP Library Granted Patent US 9,921,859
Granted Patent B2
US 9,921,859 · App. 14/966,965 · Granted Mar 20, 2018

Runtime compiler environment with dynamic co-located code execution

Inventors: Jason Mars (Ann Arbor, MI); Michael Laurenzano (Dexter, MI); Lingjia Tang (Ann Arbor, MI)
Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
G06F9/4552G06F8/443
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Quick Facts
Patent No.
US 9,921,859
App. No.
14/966,965
Granted
Mar 20, 2018
Kind
B2
Abstract

A system is provided for monitoring, regenerating and replacing the code of running applications with semantically equivalent, specialized code versions that reflect the demands of the execution environment. The system includes a co-designed compiler and runtime system that virtualizes a selected set of edges in a host program, where these edges provide hooks through which the runtime system may redirect execution into an intermediate representation utilized to optimize introspective and extrospective processes.

Claims (20)

1. A computer-implemented method of compiling a host application code for runtime execution on one or more runtime processors, the method comprising:

receiving a host application code;

virtualizing, at compile time by a static compiler, in one or more processors, one or more control edges in the host application code, the host application code comprising a plurality of cached executable functions and/or code regions, where the one or more control edges are redirection points for a subset of the plurality of executable functions and/or code regions, the redirection points being configured for (i) redirecting a second, runtime compiler out of the host application code during the runtime execution and into a co-located executable function and/or code regions for execution in place of the corresponding function of the subset of the plurality of cached executable functions and/or code regions, and (ii) redirecting code execution back into the host application code after completion of the executed cached code;

embedding, in the one or more processors, metadata into the host application code, wherein the metadata includes at least one of (i) a mapping of the subset of the plurality of executable functions and/or code regions to the one or more control edges or (ii) an intermediate representation of the host application code that encodes source level information and program analysis information; and

forming, in the one or more processors, a runtime version of the host application code to include the plurality of executable functions and/or code regions and the metadata.

2. The method of claim 1 , wherein the intermediate representation is embedded into the host application code at a binary level.

3. The method of claim 1 , wherein the metadata includes an edge virtualization table that maps the subset of the plurality of executable functions and/or code regions to the one or more control edges, wherein the edge virtualization table comprises source and target addresses for each of the one or more virtualized control edges.

4. The method of claim 1 , further comprising virtualizing the one or more control edges by establishing control edges at code branches and/or code calls within the host application code.

5. The method of claim 1 , further comprising virtualizing the one or more control edges by establishing control edges at functional calls within the host application code.

6. The method of claim 5 , further comprising virtualizing the one or more control edges by establishing control edges at functional calls where each functional call comprises a callee function, the callee function having more than one basic block.

7. A system comprising:

one or more processors and one or more memories, the one or more memories storing instructions that when executed by the one or more processors, cause the one or more processors to:

receive a host application code;

virtualize, at compile time by a static compiler, in one or more processors, one or more control edges in the host application code, the host application code comprising a plurality of executable functions and/or code regions, where the one or more control edges are redirection points for a subset of the plurality of cached executable functions and/or code regions, the redirection points being configured for ffi redirecting a second, runtime compiler out of the host application code during the runtime execution and into a co-located executable function and/or code regions for execution in place of the corresponding function of the subset of the plurality of cached executable functions and/or code regions, and (ii) redirecting code execution back into the host application code after completion of the executed cached code;

embed, in the one or more processors, metadata into the host application code, wherein the metadata includes at least one of (i) a mapping of the subset of the plurality of executable functions and/or code regions to the one or more control edges or (ii) an intermediate representation of the host application code that encodes source level information and program analysis information; and

form, in the one or more processors, a runtime version of the host application code to include the plurality of executable functions and/or code regions and the metadata.

8. The system of claim 7 , wherein the metadata includes an edge virtualization table that maps the subset of the plurality of executable functions and/or code regions to the one or more control edges, wherein the edge virtualization table comprises source and target addresses for each of the one or more virtualized control edges.

9. The system of claim 7 , wherein the one or more memories further store instructions that when executed by the one or more processors, cause the one or more processors to virtualize the one or more control edges by establishing control edges at code branches and/or code calls within the host application code.

10. The system of claim 7 , wherein the one or more memories further store instructions that when executed by the one or more processors, cause the one or more processors to virtualize the one or more control edges by establishing control edges at functional calls within the host application code.

11. The system of claim 7 , wherein the one or more memories further store instructions that when executed by the one or more processors, cause the one or more processors to virtualize the one or more control edges by establishing control edges at functional calls where each functional call comprises a callee function, the callee function having more than one basic block.

Assignments (3)
CONFIRMATORY LICENSE Recorded Feb 27, 2019
From: UNIVERSITY OF MICHIGAN
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 048458/0487 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2016
From: MARS, JASON; LAURENZANO, MICHAEL; TANG, LINGJIA
To: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
Reel/Frame 037817/0558 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2016
From: MARS, JASON; LAURENZANO, MICHAEL; TANG, LINGJIA
To: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
Reel/Frame 037789/0657 →
Continuity (2)
Provisional Application 62091297 · Dec 12, 2014
Related Publication 20160170727A1 · Jun 16, 2016