Cooling and power delivery for a wafer level computing board
A computing device includes a wafer having multiple layers, the wafer including a top layer and sublayers disposed below it, the sublayers including one or more memory devices. The computing device also includes two or more shaped retainer elements shaped to mate with and at least partially surround at least the top of the wafer and in electrical contact with one or more chips disposed on a top of the top layer and a holding device that mates with the retainer elements to provide at least power to the retaining elements. So arranged, the wafer may be cooled.
1. A computing device including:
a wafer having a top layer and a curved outer edge;
two or more shaped retainer elements each shaped to mate with and at least partially surround at least the top of the wafer and in electrical contact with one or more chips disposed on a top of the top layer;
a holding device that mates with the retainer elements to provide power to one of the retainer elements and data to another one of the retainer elements;
wherein the retainer elements are curvilinear.
2. The device of claim 1 , wherein the holding device includes two halves that are moved together to mate with the retainer elements.
3. The device of claim 2 , wherein a heat sink is attached to the top of the wafer.
4. The device of claim 3 , wherein a heat sink is attached to the bottom of the wafer.