METHOD AND STRUCTURE FOR FAN-OUT WAFER LEVEL PACKAGING

1 . A method for fan-out wafer level chip packaging, comprising:

providing a carrier substrate;

forming a strippable protective film with a plurality of openings on a surface of the carrier substrate;

forming at least one metal layer having multiple portions in the plurality of openings;

removing the carrier substrate;

mounting a plurality of chips on the metal layer and electrically connecting the chips to the metal layer;

packaging the chips and the metal layer;

forming a plurality of redistribution layers on surfaces of the metal layer to electrically connect to the metal layer; and

forming soldering balls on surfaces of the redistribution layers.

2 . The fan-out wafer level packaging method according to claim 1 , wherein:

the metal layer has a double-level structure including a first metal layer and a second metal layer;

the first metal layer is made of one of Sn, Ag, Ni, Pd, and Au;

the second metal layer is made of one of Sn, Ag, Ni, Pd, and Au;

the first metal layer is formed on a surface of the carrier substrate; and

the second metal layer is formed on the first metal layer.

3 . The fan-out wafer level chip packaging method according to claim 2 , wherein the first metal layer and the second metal layer are made of different materials.

4 . The fan-out wafer level packaging method according to claim 1 , wherein forming the plurality of redistribution layers on surface of the metal layer further includes:

forming a plurality of protective dielectric layers on a surface of the packaged structure opposite to the packaging layer to cover a portion of the metal layer; and

forming the plurality of redistribution layers on another portion of the metal layer uncovered by the protective dielectric layer;

5 . The fan-out wafer level chip packaging method according to claim 4 , wherein the redistribution layers have a single-level or a multiple-level structure.

6 . The fan-out wafer level chip packaging method according to claim 5 , wherein forming the multiple-level structure of the redistribution layers further including:

forming a plurality of protective dielectric layers on the surface of the packaged structure opposite to the packaging layer with each protective dielectric layer covering a portion of the surface area corresponding to the metal layer;

forming a plurality of redistribution layers on an uncovered portion of the surface area by the protective dielectric layers; and

repeating the above processes until all levels of redistribution layers are formed, wherein:

the multiple levels of redistribution layers are tightly linked with each other to form conductive connections for the multiple portions of the metal layer.

7 . The fan-out wafer level chip packaging method according to claim 1 , wherein the carrier substrate is made of one of glass, alumina, single-crystalline silicon, aluminum nitride, beryllium oxide, silicon carbide, and sapphire.

8 . The fan-out wafer level chip packaging method according to claim 1 , wherein the strippable protective film is one of ultraviolet film, polyethylene terephthalate film, polyethylene film, orientated polypropylene OPP film, and polyvinyl alcohol film.

9 . The fan-out wafer level chip packaging method according to claim 1 , wherein the packaging material is one of silicone resin, polyimide, phenol resin, epoxy resin, polyurethane, and acrylic resin.

10 . The fan-out wafer level chip packaging method according to claim 1 , wherein the protective dielectric layers are made of one of Cu, Ag, Sn, Ni, Pd, Au, and their alloys.

11 . The fan-out wafer level chip packaging method according to claim 1 , wherein the redistribution layers are made of one of photosensitive ink, thermosetting ink, coating, SiO2 film, ultraviolet adhesive, polyethylene terephthalate film, polyester film, polypropylene film, and polyethylene film.

12 . The fan-out wafer level chip packaging method according to claim 1 , wherein mounting the chips on the metal layer further includes:

using a CCD image alignment device to monitor deflection of the chips;

using chip claws to correct the positions of the chips; and

using a metallic needle to absorb an excess amount of soldering flux.

13 . The fan-out wafer level chip packaging method according to claim 12 , wherein the chip claws have fingers moving along four directions to correct positions of chips based on monitoring results of the CCD image alignment device.

14 . A fan-out wafer level packaged structure, comprising:

a plurality of chips having electrodes on the chips;

a strippable protective film having a plurality of openings;

a metal layer having a plurality of portions;

a plurality of wire leads;

a plurality of protective dielectric layers;

a plurality of redistribution layers;

a plurality of soldering balls; and

a packaging layer, wherein:

the metal layer is formed in the openings of the strippable protective film;

the chips are individually mounted on the metal layer;

the wire leads connect the electrodes of the chips to the metal layer;

the packaging layer encapsulates the chips, the wire leads, and a top surface of the metal layer and the strippable protective film;

the redistribution layers are electrically connected to the multiple portions of the metal layer;

the protective dielectric layers fill the spaces between the redistribution layers; and

each soldering ball is formed on an exposed surface of the corresponding redistribution layer.

15 . The fan-out wafer level packaged structure according to 14 , wherein:

each metal layer has a double-level structure including a first metal layer and a second metal layer;

the first metal layer is in contact with the packaging layer; and

the second metal layer is in contact with a redistribution layer.

16 . The fan-out wafer level packaged structure according to 14 , wherein:

the redistribution layers have a single-level or a multiple-level structure.