Interconnect structure with misaligned metal lines coupled using different interconnect layer

1. An interconnect structure, comprising:

a first metal line formed in a first interconnect layer, extending in length substantially along a first direction and ending at a first end portion;

a second metal line formed in the first interconnect layer, starting from a second end portion, extending in length substantially along the first direction and misaligned with the first metal line in the first direction; and

a first connection structure coupling the first metal line to the second metal line,

wherein

the first connection structure comprises a first end-to-end portion formed in a second interconnect layer different from the first interconnect layer, and being overlapped with the first end portion and the second end portion.

2. The interconnect structure of claim 1 , wherein

the first end-to-end portion is a single damascene via.

3. The interconnect structure of claim 1 , wherein

the first connection structure further comprises an additional portion formed in a layer different from the first interconnect layer and the second interconnect layer and coupled to the first end-to-end portion.

4. The interconnect structure of claim 3 , wherein

the additional portion has a rectangular shape having width across a width of the first metal line and a width of the second metal line.

5. The interconnect structure of claim 1 , wherein

the first end-to-end portion has a shape comprising a first edge and a second edge opposite to each other;

the first edge has a first corner and the second edge has a second corner;

the first corner being bent from substantially along the first direction to substantially along a second direction substantially orthogonal to the first direction; and

the second corner being bent from substantially along the first direction to substantially along the second direction.

6. The interconnect structure of claim 5 , wherein

the first edge further has a third corner and the second edge further has a fourth corner;

the third corner being bent from substantially along the second direction to substantially along the first direction; and

the fourth corner being bent from substantially along the second direction to substantially along the first direction.

7. The interconnect structure of claim 5 , wherein

a width between portions of the first edge and the second edge along the first direction is not substantially wider than a width of one of the first end portion and the second end portion overlapped with a portion of the shape defined by the portions of the first edge and the second edge.

8. The interconnect structure of claim 5 , further comprising:

a third metal line formed in the first interconnect layer, extending in length substantially along the first direction and adjacent to one of the first metal line and the second metal line,

wherein

one of the first end portion and the second end portion corresponding to the one of the first metal line and the second metal line and overlapped with a portion of the shape defined by portions of the first edge and the second edge along the first direction is not beyond the third metal line in the first direction.

9. The interconnection structure of claim 1 , further comprising:

a third metal line formed in the first interconnect layer and adjacent to the first metal line, and extending in length substantially along the first direction;

a fourth metal line formed in the first interconnect layer and adjacent to the second metal line, extending in length substantially along the first direction and aligned to the third metal line in the first direction; and

a second connection structure coupling the third metal line to the fourth metal line using a third interconnect layer different from the first interconnect layer and the second interconnect layer.

10. A semiconductor chip, comprising:

an array cell comprising:

a first metal line formed in a first interconnect layer and extending substantially along a first direction;

an accessing circuit configured to access the array cell and comprising:

a second metal line formed in the first interconnect layer and extending substantially along the first direction; and

a first connection structure coupling the first metal line to the second metal line using a second interconnect layer different from the first interconnect layer,

wherein the coupled first metal line, second metal line and first connection structure serve as an accessing line of the array cell.

11. The semiconductor chip of claim 10 , wherein

the first connection structure comprises a first end-to-end portion formed in the second interconnect layer; and

the first end-to-end portion is overlapped with the first metal line and the second metal line.

12. The semiconductor chip of claim 11 , wherein

the first connection structure further comprises an additional portion formed in a layer different from the first interconnect layer and the second interconnect layer and coupled to the first end-to-end portion.

13. The semiconductor chip of claim 12 , wherein

the additional portion has a rectangular shape having width across a width of the first metal line and a width of the second metal line.

14. The semiconductor chip of claim 11 , wherein the first end-to-end portion has a shape comprising a first edge and a second edge opposite to each other;

the first edge has a first corner and the second edge has a second corner;

the first corner being bent from substantially along the first direction to substantially along a second direction substantially orthogonal to the first direction; and

the second corner being bent from substantially along the first direction to substantially along the second direction.

15. The semiconductor chip of claim 14 , wherein

the first edge further has a third corner and the second edge further has a fourth corner;

the third corner being bent from substantially along the second direction to substantially along the first direction; and

the fourth corner being bent from substantially along the second direction to substantially along the first direction.

16. The semiconductor chip of claim 14 , wherein

a width between portions of the first edge and the second edge along the first direction is not substantially wider than a width at where one of the first metal line and the second metal line is overlapped with a portion of the shape defined by the portions of the first edge and the second edge.

17. The semiconductor chip of claim 14 , wherein

a third metal line formed in the first interconnect layer, extending in length substantially along the first direction and adjacent to one of the first metal line and the second metal line,

wherein

a portion of the one of the first metal line and the second metal line at where the one of the first metal line and the second metal line is overlapped with a portion of the shape defined by portions of the first edge and the second edge along the first direction is not beyond the third metal line in the first direction.

18. The semiconductor chip of claim 10 , wherein

the first connection structure comprises a single damascene via which is overlapped with the first metal line and the second metal line.

19. The semiconductor chip of claim 10 , wherein

the array cell further comprises a third metal line formed in the first interconnect layer and extending substantially along the first direction;

the accessing circuit further comprises a fourth metal line formed in the first interconnect layer and extending substantially along the first direction; and

the circuit further comprises a second connection structure coupling the third metal line to the fourth metal line using a third interconnect layer different from the first interconnect layer and the second interconnect layer for forming a power supply node for the array cell.

20. A layout, comprising:

a first interconnect layer comprising:

a first metal line extending in length substantially along a first direction and ending at a first end portion;

a second metal line starting from a second end portion, extending in length substantially along the first direction and misaligned with the first metal line in the first direction; and

a second interconnect layer different from the first interconnect layer, wherein the second interconnect layer comprises:

a first shape overlapping with the first end portion and the second end portion.

21. The layout of claim 20 , wherein

the first shape is a single shape overlapping with both the first end portion and the second end portion.

22. The layout of claim 20 , further comprising:

an additional shape formed in a layer different from the first interconnect layer and the second interconnect layer and overlapped with the first shape.

23. The layout of claim 20 , wherein

the first shape comprises a first edge and a second edge opposite to each other;

the first edge has a first corner and the second edge has a second corner;

the first corner being bent from substantially along the first direction to substantially along a second direction substantially orthogonal to the first direction; and

the second corner being bent from substantially along the first direction to substantially along the second direction.

24. The layout of claim 20 , wherein

the first edge further has a third corner and the second edge further has a fourth corner;

the third corner being bent from substantially along the second direction to substantially along the first direction; and

the fourth corner being bent from substantially along the second direction to substantially along the first direction.