Electronic circuits including a MOSFET and a dual-gate JFET
Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.
1. A MOS device comprising:
a substrate including a first well defined within the substrate, the first well characterized by a top surface and having, defined within the first well—
a bottom gate,
a first channel defined between the bottom gate and the top surface,
a first source,
a first drain,
a second drain between the first drain and the first source,
a first gate between the first drain and the second drain, and
a gap between the first source and the second drain;
a dielectric layer disposed above the top surface of the first well and aligned with the gap; and
a second gate disposed above the dielectric layer and aligned with the gap.
2. The MOS device of claim 1 further comprising a first sidewall defined within the first well and disposed between the first gate and the second gate, the first sidewall being joined to the bottom gate.
3. The MOS device of claim 2 wherein the bottom gate and the first sidewall have a same doping.
4. The MOS device of claim 2 further comprising a second sidewall exposed at the top surface and also joined to the bottom gate, the bottom gate and two sidewalls defining a second well within the first well.
5. The MOS device of claim 4 further comprising a second source disposed within the second well such that the first top gate is disposed between the first drain and the second source.
6. The MOS device of claim 5 wherein the second drain is electrically coupled to the second source.
7. The MOS device of claim 5 wherein the first channel is disposed within the second well.
8. The MOS device of claim 4 further comprising a second channel disposed within the first well, the first and second channels comprising different dopings.
9. The MOS device of claim 1 further comprising a second channel disposed within the first well, the first and second channels comprising different dopings.