Implementation of long-channel thick-oxide devices in vertical transistor flow

1. A method for fabricating a semiconductor structure, the method comprising:

forming a structure comprising a substrate, a counter-doped layer on the substrate, and a heavily doped source contact layer on a side of the counter-doped layer opposite the substrate;

forming an oxide layer on a side of the heavily doped source contact layer opposite the counter-doped layer, wherein the oxide layer has a vertical dimension that is a difference between a length of a long channel thick oxide device and a length of a short channel non-thick oxide device;

removing a portion of the oxide layer from a first region of the structure; and

epitaxially growing the heavily doped source contact layer in the first region following the removal of the portion of the oxide layer in the first region.

2. The method of claim 1 further comprising:

removing the remainder of the oxide layer;

forming a first spacer layer on a side of the heavily doped source contact layer opposite the counter-doped layer;

forming a replacement gate on a side of the first spacer layer opposite the heavily doped source contact layer;

forming a second spacer layer on a side of the replacement gate opposite the first spacer layer; and

forming a top oxide layer on a side of the second spacer layer opposite the replacement layer.

3. The method of claim 2 further comprising forming a shallow trench isolation between the first region and a second region that extends from a top surface of the top oxide layer to partially into the substrate.

4. The method of claim 3 further comprising: forming a first channel in the first region of the structure, the first channel extending from the top surface of the top oxide layer down to a top surface of the heavily doped source contact layer; and forming a second channel in the second region of the structure, the second channel extending from the top surface of the top oxide layer down to a top surface of the heavily doped source contact layer.

5. The method of claim 4 further comprising:

forming a protective layer on exposed portions of the replacement gate within the first channel; and

forming a protective layer on exposed portions of the replacement gate within the second channel.

6. The method of claim 5 further comprising:

epitaxially growing a first channel layer up from the top surface of the heavily doped source contact layer, the first channel layer filling the first channel; and

epitaxially growing a second channel layer up from the top surface of the heavily doped source contact layer, the second channel layer filling the second channel.

7. The method of claim 6 further comprising:

recessing the first and second channel layers, the recessing leaving a first portion of the first and second channel layers above the second spacer layer;

after the recessing, forming a first mask above and in contact with the first channel layer and forming a second mask above and in contact with second channel layer;

after forming the first and second masks, removing the top oxide layer exposing the first portion of the first and second channel layers; and

performing a lateral etch of the first portion of the first and second channel layers, the lateral etch narrowing the first portion of the first and second channel layers.

8. The method of claim 7 further comprising:

forming a first drain region and second drain region on the first and second portions of the first and second channel layers, respectively.

9. The method of claim 8 further comprising:

forming a high-k metal gate structure on and in contact with the exposed sidewalls of the first channel layer.

10. The method of claim 9 further comprising:

depositing a metal gate fill material in the first region of the semiconductor structure.

11. The method of claim 10 further comprising:

forming a thick oxide on and in contact with the exposed sidewalls of the second channel layer;

forming a high-k metal gate structure on and in contact with the thick oxide; and

forming a work function metal gate structure on and in contact with the high-k metal gate structure.

12. The method of claim 11 further wherein the hick oxide has an equivalent oxide thickness of about 1 to about 5 nanometers.

13. The method of claim 12 further comprising:

depositing a metal gate fill material in the second region of the semiconductor structure; and

recessing the metal gate fill material in both the first region and the second region.

14. A method for fabricating a semiconductor structure, the method comprising:

forming a structure comprising a substrate, a counter-doped layer on the substrate, and a heavily doped source contact layer on a side of the counter-doped layer opposite the substrate;

forming an oxide layer on a side of the heavily doped source contact layer opposite the counter-doped layer, wherein the oxide layer has a vertical dimension that is a difference between a length of a long channel thick oxide device and a length of a short channel non-thick oxide device;

removing a portion of the oxide layer from a first region of the structure;

epitaxially growing the heavily doped source contact layer in the first region following the removal of the portion of the oxide layer in the first region;

forming a shallow trench isolation between the first region and a second region that extends from a top surface of the structure to partially into the substrate;

forming a first channel in the first region of the structure, the first channel extending from the top surface of the structure down to a top surface of the heavily doped source contact layer;

forming a second channel in the second region of the structure, the second channel extending from the top surface of the structure down to a top surface of the heavily doped source contact layer;

epitaxially growing a first channel layer up from the top surface of the heavily doped source contact layer, the first channel layer filling the first channel; and

epitaxially growing a second channel layer up from the top surface of the heavily doped source contact layer, the second channel layer filling the second channel.