Semiconductor device
A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
1. A semiconductor device comprising:
word lines;
a pair of bit lines;
static type memory cells coupled to the word lines and the pair of bit lines so that one static type memory cell is coupled to one word line and the pair of data lines, the static type memory cells each including a first Metal insulator Semiconductor Field Effect Transistor (MISFET);
a sense amplifier circuit which amplifies data read out to the pair of bit lines from one memory cell selected by one word line, an amplification operation thereof being controlled by an enable signal; and
a control circuit which includes second MISFETs gate lengths thereof being longer than a gate length of the first MISFET
wherein the control circuit is configured to delay a control signal with the second MISFETs and generate the enable signal based on the delayed control signal.
2. A semiconductor device according to claim 1 ,
wherein the control circuit includes a timing adjustment circuit which includes a wiring line and the second MISFETs coupled to the wiring line.
3. A semiconductor device according to claim 2 ,
wherein the wiring line includes:
a first line as an outward line arranged collaterally with the pair of bit lines and coupled to sources or drains of a part of the second MISFETs, and
a second line as a homeward line arranged collaterally with the pair of bit lines and coupled to sources or drains of the other of the second MISFETs.
4. A static random access memory in a semiconductor device, the static random access memory comprising:
word lines;
a pair of bit lines;
memory cells coupled to the word lines and the pair of bit lines so that one memory cell is coupled to one word line and the pair of data lines, the memory cells each including a first Metal insulator Semiconductor Field Effect Transistor (MISFET);
an address control circuit coupled to the word lines, the address control circuit selecting one word line based on an address signal, a selection operation thereof being control by a control signal;
a sense amplifier circuit which amplifies data read out to the pair of bit lines from one memory cell selected by one word line, an amplification operation thereof being controlled by an enable signal; and
a control circuit which includes second MISFETs gate lengths thereof being longer than a gate length of the first MISFET and which provides the enable signal by delaying the control signal with the second MISFETs,
wherein the control circuit includes a timing adjustment circuit which includes a wiring line and the second MISFETs coupled to the wiring line.
5. A static random access memory according to claim 4 ,
wherein the wiring line includes:
a first line as an outward line arranged collaterally with the pair of bit lines and coupled to sources or drains of a part of the second MISFETs, and
a second line as a homeward line arranged collaterally with the pair of bit lines and coupled to sources or drains of the other of the second MISFETs.
6. A static random access memory according to claim 4 ,
wherein the timing adjustment circuit is arranged between the address control circuit and the pair of data lines.
7. A static random access memory according to claim 6 ,
wherein the wiring line includes:
a first line as an outward line arranged collaterally with the pair of bit lines and coupled to sources or drains of a part of the second MISFETs, and
a second line as a homeward line arranged collaterally with the pair of bit lines and coupled to sources or drains of the other of the second MISFETs.
8. A static random access memory according to claim 4 , wherein the control circuit is configured to delay the control signal with the second MISFETs and generate the enable signal based on the delayed control signal.
9. A semiconductor device comprising:
a central processing unit; and
a static random access memory coupled to the central processing unit,
wherein the static random access memory includes:
word lines;
a pair of bit lines;
memory cells coupled to the word lines and the pair of bit lines so that one memory cell is coupled to one word line and the pair of data lines, the memory cells each including a first Metal insulator Semiconductor Field Effect Transistor (MISFET);
an address control circuit coupled to the word lines, the address control circuit selecting one word line based on an address signal from the central processing unit, a selection operation thereof being control by a control signal;
a sense amplifier circuit which amplifies data read out to the pair of bit lines from one memory cell selected by one word line, an amplification operation thereof being controlled by an enable signal; and
a control circuit which includes second MISFETs gate lengths thereof being longer than a gate length of the first MISFET and which provides the enable signal by delaying the control signal with the second MISFETs,
wherein the control circuit includes a timing adjustment circuit which includes a wiring line and the second MISFETs coupled to the wiring line.
10. A semiconductor device according to claim 9 ,
wherein the wiring line includes:
a first line as an outward line arranged collaterally with the pair of bit lines and coupled to sources or drains of a part of the second MISFETs, and
a second line as a homeward line arranged collaterally with the pair of bit lines and coupled to sources or drains of the other of the second MISFETs.
11. A semiconductor device according to claim 9 ,
wherein the timing adjustment circuit is arranged between the address control circuit and the pair of data lines.
12. A semiconductor device according to claim 11 ,
wherein the wiring line includes:
a first line as an outward line arranged collaterally with the pair of bit lines and coupled to sources or drains of a part of the second MISFETs, and
a second line as a homeward line arranged collaterally with the pair of bit lines and coupled to sources or drains of the other of the second MISFETs.
13. A semiconductor device according to claim 9 , wherein the control circuit is configured to delay the control signal with the second MISFETs and generate the enable signal based on the delayed control signal.