Apparatus and method for multi-bit error detection and correction
An apparatus and method are described for multi-bit error correction and detection. For example, one embodiment of a processor comprises: error detection logic to detect one or more errors in data when reading the data from a storage device, the data being read from the storage device with parity codes and error correction codes (ECCs); error correction logic to correct the errors detected by the error detection logic; and a matrix usable by both the error detection logic to detect the one or more errors and the error correction logic to correct the errors, the matrix constructed into N regions, each region having M columns forming a geometric sequence, wherein each successive region is a shifted version of a prior region.
1. A processor comprising:
error detection circuitry to detect one or more errors in data when reading the data from a storage device;
error correction circuitry to correct some errors detected by the error detection circuitry; and
the error detection circuitry and error correction circuitry to utilize error detection/correction data from a matrix to detect and correct the one or more errors, respectively;
the matrix constructed into N regions, each region having M columns forming a geometric sequence, wherein each successive region is a shifted version of a prior region such that a plurality of the M columns are reused in each successive region; and
the error detection/correction data in the matrix comprising parity data and ECC data, the error detection circuitry to identify a particular region containing an error using the parity data and the error correction circuitry to responsively focus on the region identified with the parity data when performing error corrections using the ECC data.
2. The processor as in claim 1 wherein each region comprises one of four quadrants and wherein each of the four quadrants comprises 32 columns.
3. The processor as in claim 2 wherein a second of the four quadrants comprises a left-shift of a first quadrant, a third of the four quadrants comprises a left-shift of the second quadrant, and a fourth of the four quadrants comprises a left-shift of the third quadrant.
4. The processor as in claim 3 wherein each of the four quadrants is to be associated with a 32 bit region of data stored in the storage device.
5. The processor as in claim 4 wherein the error detection circuitry is to detect the error in the first region with the parity bit associated with one of the four quadrants associated with that region, wherein the error correction circuitry is to responsively identify and use the ECC code to correct the error in the one of the four quadrants.
6. The processor as in claim 5 wherein the matrix is constructed to allow the error correction circuitry to correct all single-bit errors and consecutive double-bit errors.
7. The processor as in claim 6 wherein the matrix comprises a unique error syndrome for each error.
8. The processor as in claim 7 wherein for single-bit errors, the syndrome equals a corresponding matrix column.
9. The processor as in claim 7 wherein for double-bit errors, the syndrome equals an XOR of two corresponding matrix columns.
10. The processor as in claim 7 wherein the matrix is to be validated to ensure syndrome uniqueness for each error syndrome.
11. The processor as in claim 1 wherein the storage device comprises a register, processor buffer, cache memory or system memory.
12. A method comprising:
reading error detection/correction data from a matrix;
detecting and correcting one or more errors in data when reading the data from a storage device; and
wherein the matrix is constructed into N regions, each region having M columns forming a geometric sequence, wherein each successive region is a shifted version of a prior region such that a plurality of the M columns are reused in each successive region; and
the error detection/correction data in the matrix comprising parity data and ECC data, wherein the detecting comprises identifying a particular region containing an error using the parity data; and the correcting comprises responsively focusing on the region identified with the parity data when performing error corrections using the ECC data.
13. The method as in claim 12 wherein each region comprises one of four quadrants and wherein each of the four quadrants comprises 32 columns.
14. The method as in claim 13 wherein a second of the four quadrants comprises a left-shift of a first quadrant, a third of the four quadrants comprises a left-shift of the second quadrant, and a fourth of the four quadrants comprises a left-shift of the third quadrant.
15. The method as in claim 14 wherein each of the four quadrants is to be associated with a 32 bit region of data stored in the storage device.
16. The method as in claim 15 wherein the error is to be detected in the first region with the parity bit associated with one of the four quadrants associated with that region, wherein the ECC code is to be used to correct the error in the one of the four quadrants associated with the first region.
17. The method as in claim 16 wherein the matrix is constructed to provide for the correction of all single-bit errors and consecutive double-bit errors.
18. The method as in claim 17 wherein the matrix comprises a unique error syndrome for each error.
19. The method as in claim 18 wherein for single-bit errors, the syndrome equals a corresponding matrix column.
20. The method as in claim 18 wherein for double-bit errors, the syndrome equals an XOR of two corresponding matrix columns.
21. The method as in claim 18 wherein the matrix is to be validated to ensure syndrome uniqueness for each error syndrome.
22. The processor as in claim 12 wherein the storage device comprises a register, processor buffer, cache memory or system memory.
23. A system comprising:
a system memory to store instructions and data;
a plurality of functional units or cores to execute the instructions and process the data;
a graphics processor to perform graphics operations in response to certain instructions;
a network interface for receiving and transmitting data over a network;
an interface for receiving user input from a mouse or cursor control device; and
an electronic circuit comprising:
error detection circuitry to detect one or more errors in data when reading the data from a storage device;
error correction circuitry to correct some errors detected by the error detection circuitry; and
the error detection circuitry and error correction circuitry to utilize error detection/correction data from a matrix to detect and correct the one or more errors, respectively;
the matrix constructed into N regions, each region having M columns forming a geometric sequence, wherein each successive region is a shifted version of a prior region such that a plurality of the M columns are reused in each successive region; and
the error detection/correction data in the matrix comprising parity data and ECC data, the error detection circuitry to identify a particular region containing an error using the parity data and the error correction circuitry to responsively focus on the region identified with the parity data when performing error corrections using the ECC data.
24. The system as in claim 23 wherein each region comprises one of four quadrants and wherein each of the four quadrants comprises 32 columns.
25. The system as in claim 24 wherein a second of the four quadrants comprises a left-shift of a first quadrant, a third of the four quadrants comprises a left-shift of the second quadrant, and a fourth of the four quadrants comprises a left-shift of the third quadrant.