Fast read speed memory device
View Patent ↗A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
1. A memory cell comprising:
a first resistive memory element;
a second resistive memory element electrically coupled with the first resistive memory element at a common node; and
a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
2. The memory cell of claim 1 , wherein the switching element comprises a tristate driver that is left floating during a programming operation based on a program enable signal.
3. The memory cell of claim 1 , wherein the switching element comprises a first transistor and a second transistor coupled in series, the memory cell further comprising:
a third transistor coupled in series between a voltage supply source and the first transistor; and
a fourth transistor coupled in series between the second transistor and ground.
4. The memory cell of claim 3 , wherein a program enable signal is applied to a gate terminal of the third transistor and an inverse of the program enable signal is applied to a gate terminal of the fourth transistor.
5. The memory cell of claim 3 , wherein the switching element further comprises a fifth transistor coupled in parallel with the first transistor and a sixth transistor coupled in parallel with the second transistor, the fifth transistor and the sixth transistor to latch a read value from the first resistive memory element and the second resistive memory element.
6. The memory cell of claim 1 , wherein the first resistive memory element has a first polarity, and wherein the second resistive memory element has a second polarity that is different than the first polarity.
7. The memory cell of claim 1 , wherein the first resistive memory element comprises a first terminal electrically coupled with the common node and a second terminal electrically coupled with a write word line signal, and wherein the second resistive memory element comprises a third terminal electrically coupled with the common node and a fourth terminal electrically coupled with a write bit line signal.
8. A memory device comprising:
a plurality of resistive memory cells, each resistive memory cell comprising:
a first resistive memory element;
a second resistive memory element electrically coupled with the first resistive memory element at a common node between the first resistive memory element and the second resistive memory element; and
a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
9. The memory device of claim 8 , wherein the switching element comprises a tristate driver that is left floating during a programming operation based on a program enable signal.
10. The memory device of claim 9 , wherein the switching element comprises a first transistor and a second transistor coupled in series, each resistive memory cell further comprising:
a third transistor coupled in series between a voltage supply source and the first transistor; and
a fourth transistor coupled in series between the second transistor and ground.
11. The memory device of claim 10 , wherein a program enable signal is applied to a gate terminal of the third transistor and an inverse of the program enable signal is applied to a gate terminal of the fourth transistor.
12. The memory device of claim 10 , wherein the switching element further comprises a fifth transistor coupled in parallel with the first transistor and a sixth transistor coupled in parallel with the second transistor, the fifth transistor and the sixth transistor to latch a read value from the first resistive memory element and the second resistive memory element.
13. The memory device of claim 8 , wherein the first resistive memory element has a first polarity, and wherein the second resistive memory element has a second polarity that is different than the first polarity.
14. The memory device of claim 8 , wherein the first resistive memory element comprises a first terminal electrically coupled with the common node and a second terminal electrically coupled with a write word line signal, and wherein the second resistive memory element comprises a third terminal electrically coupled with the common node and a fourth terminal electrically coupled with a write bit line signal.
15. A memory device comprising:
a plurality of inputs lines to receive an input signal, the input signal to identify a memory cell of a plurality of memory cells to be programmed during a programming operation; and
the plurality of memory cells to store data, wherein each of the plurality of memory cells comprises:
a first resistive memory element;
a second resistive memory element electrically coupled with the first resistive memory element at a common node; and
a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
16. The memory device of claim 15 , wherein the switching element comprises a tristate driver that is left floating during a programming operation based on a program enable signal.
17. The memory device of claim 15 , wherein the switching element comprises a first transistor and a second transistor coupled in series, the memory device further comprising:
a third transistor coupled in series between a voltage supply source and the first transistor of each of the plurality memory cells; and
a fourth transistor coupled in series between the second transistor of each of the plurality of memory cells and ground.
18. The memory device of claim 17 , wherein a program enable signal is applied to a gate terminal of the third transistor and an inverse of the program enable signal is applied to a gate terminal of the fourth transistor.
19. The memory device of claim 15 , wherein the first resistive memory element has a first polarity, and wherein the second resistive memory element has a second polarity that is different than the first polarity.
20. The memory device of claim 15 , wherein the first resistive memory element comprises a first terminal electrically coupled with the common node and a second terminal electrically coupled with a respective write word line signal, and wherein the second resistive memory element comprises a third terminal electrically coupled with the common node and a fourth terminal electrically coupled with a common write bit line signal.