Patent Assignment
Reel/Frame 045984/0845
Assignment of Assignor's Interest
Recorded: 2018-05-04
Pages: 7
Assignor
RAMBUS INC.
Executed: 2018-05-04
Assignee
HEFEI RELIANCE MEMORY LIMITED
ROOM A-08, 14TH FLOOR, PLAZA A, BUILDING J1, INNOVATIVE INDUSTRIAL PARK PHASE II, HIGH-TECH ZONE, HEFEI, CHINA
Covered Properties
(71)
Techniques for Initializing Resistive Memory Devices
PCT:
PCT/US2017/047902 ↗
Adaptive Memory Cell Write Conditions
PCT:
PCT/US2017/052761 ↗
Rram Process Intergration Scheme and Cell Structure with Reduced Masking Operations
PCT:
PCT/US2017/061393 ↗
Non-Volatile Memory Structure with Positioned Doping
PCT:
PCT/US2017/061394 ↗
Rram Write
PCT:
PCT/US2017/067349 ↗
Multi-Resistive State Element with Reactive Metal
Memory Element Having Islands
Memory Using Variable Tunnel Barrier Widths
Semiconductor Chip Having Pollished and Ground Bottom Surface Portions
Semiconductor Device Having a Silicon Layer in a Gate Electrode
Semiconductor Device Including a Stacked Capacitor
Method of Manufacturing Semiconductor Device Having Planarized Interlayer Insulating Film
Semiconductor Chip with a Porous Single Crystal Layer and Manufacturing Method of the Same
Mask Data Creation Method
Semiconductor Device with Capacitor Suppressing Leak Current
Multi-Resistive State Element with Reactive Metal
Method for Controlling Thickness Distribution of a Film
Semiconductor Apparatus
Method of Manufacturing Semiconductor Device
Manufacturing Method for Increasing Product Yield of Memory Devices Suffering from Source/Drain Junction Leakage
Semiconductor Device and Method for Manufacturing the Same
Method for Forming a Nitrogen-Containing Gate Insulating Film
Semiconductor Device and Method of Forming the Same
Manufacturing Method of Semiconductor Device
Method for Fabricating a Cylindrical Capacitor Including Implanting Impurities into the Upper Sections of the Lower Electrode to Prevent the Formation of Hemispherical Grain Silicon on the Upper Sections.
Method for Manufacturing a Semiconductor Device
Polishing Apparatus and Method of Reconditioning Polishing Pad
Integrated circuits and methods to control access to multiple layers of memory
Semiconductor Device Manufacturing Method and Semiconductor Device
Method for Fabricating Multi-Resistive State Memory Devices
Semiconductor Device Having Silicon Layer in a Gate Electrode
Multi-Resistive State Memory Device with Conductive Oxide Electrodes
Fuse Elements Based on Two-Terminal Re-Writeable Non-Volatile Memory
Semiconductor Apparatus
Continuous Plane of Thin-Film Materials for a Two-Terminal Cross-Point Memory
Threshold Device for a Memory Array
Memory Element with a Reactive Metal Layer
Non Volatile Memory Device Ion Barrier
Method For Fabricating Multi Resistive State Memory Devices
Semiconductor Apparatus
Planar Resistive Memory Integration
Resistance Change Memory Cell Circuits and Methods
Planar Resistive Memory Integration
Resistance Memory Cell
Memory Element with a Reactive Metal Layer
Fast Read Speed Memory Device
System and Method for Performing Memory Operations on Rram Cells
Multi-Layered Conductive Metal Oxide Structures and Methods for Facilitating Enhanced Performance Characteristics of Two-Terminal Memory Cells
Two-Terminal Reversibly Switchable Memory Device
Resistance Change Memory Cell Circuits and Methods
1T-1R Architecture for Resistive Random Access Memory
1D-2R Memory Architecture
Distributed Cascode Current Source for Rram Set Current Limitation
Two-Terminal Reversibly Switchable Memory Device
Memory Element with a Reactive Metal Layer
Resistance Change Memory Cell Circuits and Methods
Fast Read Speed Memory Device
2T-1R Architecture for Resistive Ram
Resistance Memory Cell
1T-1R Architecture for Resistive Random Access Memory
Distributed Cascode Current Source for Rram Set Current Limitation
Multi-Layered Conductive Metal Oxide Structures and Methods for Facilitating Enhanced Performance Characteristics of Two-Terminal Memory Cells
Fast Read Speed Memory Device
Resistance Change Memory Cell Circuits and Methods
System and Method for Performing Memory Operations on Rram Cells
Memory Element with a Reactive Metal Layer
Resistance Change Memory Cell Circuits and Methods
Two-Terminal Reversibly Switchable Memory Device
Memory Element with a Reactive Metal Layer
Multi-Layered Conductive Metal Oxide Structures and Methods for Facilitating Enhanced Performance Characteristics of Two-Terminal Memory Cells
1T-1R Architecture for Resistive Random Access Memory
Related Assignments
(12)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement
Apr 13, 2009
From: UNITY SEMICONDUCTOR CORPORATION
To: GOLD HILL CAPITAL
Reel/Frame 023129/0669 →
Release
Apr 9, 2012
From: SILICON VALLEY BANK; GOLD HILL CAPITAL
To: UNITY SEMICONDUCTOR, INC.
Reel/Frame 028132/0675 →
Assignment of Assignor's Interest
Mar 20, 2013
From: ELPIDA MEMORY, INC.
To: RAMBUS INC.
Reel/Frame 030049/0831 →
Assignment of Assignor's Interest
Mar 20, 2013
From: ELPIDA MEMORY, INC.
To: RAMBUS INC.
Reel/Frame 030049/0724 →
Assignment of Assignor's Interest
Jun 3, 2013
From: ELPIDA MEMORY, INC.
To: RAMBUS INC.
Reel/Frame 030534/0994 →
Assignment of Assignor's Interest
Mar 10, 2014
From: HAUKNESS, BRENT STEVEN
To: RAMBUS INC.
Reel/Frame 032395/0188 →
Assignment of Assignor's Interest
Mar 10, 2014
From: HAUKNESS, BRENT STEVEN
To: RAMBUS INC.
Reel/Frame 032395/0170 →
Assignment of Assignor's Interest
Nov 7, 2017
From: HAUKNESS, BRENT; LU, ZHICHAO
To: RAMBUS INC
Reel/Frame 044058/0301 →
Assignment of Assignor's Interest
Jan 11, 2018
From: HAUKNESS, BRENT STEVEN; LU, ZHICHAO
To: RAMBUS INC
Reel/Frame 044599/0717 →
Assignment of Assignor's Interest
Apr 27, 2018
From: LU, ZHICHAO; HAUKNESS, BRENT; BRONNER, GARY
To: RAMBUS INC
Reel/Frame 045656/0010 →
Assignment of Assignor's Interest
Apr 27, 2018
From: LU, ZHICHAO; HAUKNESS, BRENT; BRONNER, GARY
To: RAMBUS INC
Reel/Frame 045655/0669 →
Nunc Pro Tunc Assignment
Jun 21, 2018
From: UNITY SEMICONDUCTOR CORPORATION
To: HEFEI RELIANCE MEMORY LIMITED
Reel/Frame 046407/0710 →