Patent Assignment
Reel/Frame 028132/0675
Release
Recorded: 2012-04-09
Pages: 14
Assignee
UNITY SEMICONDUCTOR, INC.
1050 ENTERPRISE WAY SUITE 700, SUNNYVALE, CALIFORNIA, 94089
Covered Properties
(128)
Memory Array of a Non-Volatile Ram
Non-Volatile Memory with a Single Transistor and Resistive Memory Element
Multi-Output Multiplexor
Cross Point Memory Array Using Multiple Modes of Operation
Providing a Reference Voltage to a Cross Point Memory Array
Cross Point Memory Array Using Multiple Thin Films
Patent:
6,753,561 →
Application:
10/330,512 →
Cross Point Memory Array with Memory Plugs Exhibiting a Characteristic Hysteresis
Cross Point Memory Array Using Distinct Voltages
Multiplexor Having a Reference Voltage on Unselected Lines
High-Density Nvram
Low Temperature Deposition of Complex Metal Oxides (Cmo) Memory Materials for Non-Volatile Memory Integrated Circuits
Laser Annealing of Complex Metal Oxides (Cmo) Memory Materials for Non-Volatile Memory Integrated Circuits
Rewritable Memory with Non-Linear Memory Element
Multi-Resistive State Material That Uses Dopants
Multi-Layer Conductive Memory Device
Conductive Memory Stack with Non-Uniform Width
Conductive Memory Stack with Sidewall
Re-Writable Memory with Multiple Memory Layers
Line Drivers That Use Minimal Metal Layers
Layout of Driver Sets in a Cross Point Memory Array
Cross Point Memory Array with Fast Access Time
Line Drivers That Fit Within a Specified Line Pitch
2-Terminal Trapped Charge Memory Device with Voltage Switchable Multi-Level Resistance
Resistive Memory Device with a Treated Interface
Adaptive Programming Technique for a Re-Writable Conductive Memory Device
Conductive Memory Device with Conductive Oxide Electrodes
Conductive Memory Array Having Page Mode and Burst Mode Write Capability
Conductive Memory Array Having Page Mode and Burst Mode Read Capability
Memory Array with High Temperature Wiring
Multi-Resistive State Element with Reactive Metal
Memory Element Having Islands
Two Terminal Memory Array Having Reference Cells
Multiple Modes of Operation in a Cross Point Array
Discharge of Conductive Array Lines in Fast Memory
Memory Using Variable Tunnel Barrier Widths
Cross Point Array Using Distinct Voltages
Enhanced Functionality in a Two-Terminal Memory Array
Line Drivers That Fits Within a Specified Line Pitch
Movable Terminal in a Two Terminal Memory Array
Cross Point Memory Array Exhibiting a Characteristic Hysteresis
Memory Array of a Non-Volatile Ram
Non-Volatile Memory with a Single Transistor and Resistive Memory Element
Memory using mixed valence conductive oxides
Application:
11/095,026 →
Publication:
US 2006/0171200
Re-Writable Memory with Multiple Memory Layers
High-Density Nvram
Adaptive Programming Technique for a Re-Writable Conductive Memory Device
Providing a Reference Voltage to a Cross Point Memory Array
Storage Controller for Multiple Configurations of Vertical Memory
Conductive Memory Stack with Non-Uniform Width
Conductive Memory Device with Conductive Oxide Electrodes
Patent:
7,400,006 →
Application:
11/405,958 →
Cross Point Memory Array with Fast Access Time
Serial Memory Interface
Multi-Resistive State Element with Reactive Metal
Performing Data Operations Using Non-Volatile Third Dimension Memory
Two Terminal Memory Array Having Reference Cells
Memory Power Management
Scaleable Memory Systems Using Third Dimension Memory
Sensing a Signal in a Two-Terminal Memory Array Having Leakage Current
Two-Cycle Sensing in a Two-Terminal Memory Array Having Leakage Current
Oxygen Depleted Etching Process
Application:
11/584,876 →
Publication:
US 2007/0105390
Providing a Reference Voltage to a Cross Point Memory Array
Fast Data Access Through Page Manipulation
Two Terminal Memory Array Having Reference Cells
Conductive Memory Stack with Sidewall
Two Terminal Memory Array Having Reference Cells
Two Terminal Memory Array Having Reference Cells
Continuous Plane of Thin-Film Materials for a Two-Terminal Cross-Point Memory
Multi-Step Selective Etching for Cross-Point Memory
Continuous Plane of Thin-Film Materials for a Two-Terminal Cross-Point Memory
Low Read Current Architecture for Memory
Multiple-Type Memory
Circuitry and Method for Indicating a Memory
Memory Emulation in an Image Capture Device
Memory Emulation in an Electronic Organizer
Memory Emulation in a Cellular Telephone
Memory Emulation Using Resistivity-Sensitive Memory
Planar Third Dimensional Memory with Multi-Port Access
Integrated Circuits and Methods to Compensate for Defective Memory in Multiple Layers of Memory
Disturb Control Circuits and Methods to Control Memory Disturbs Among Multiple Layers of Memory
Emulation of a Nand Memory System
Combined Memories in Integrated Circuits
Memory access protection
Application:
12/004,734 →
Publication:
US 2009/0164744
Media Player with Non-Volatile Memory
Non-volatile memory compiler
Application:
12/004,740 →
Publication:
US 2009/0164203
Method and System for Accessing Non-Volatile Memory
Memory Sanitization
Application:
12/005,259 →
Publication:
US 2009/0172251
Non-volatile processor register
Application:
12/005,685 →
Publication:
US 2009/0172350
Non-Volatile memories in interactive entertainment systems
Application:
12/005,687 →
Publication:
US 2009/0171650
Field Programmable Gate Arrays Using Resistivity Sensitive Memories
Radio frequency identification transponder memory
Application:
12/006,187 →
Publication:
US 2009/0167496
State Machines Using Resistivity-Sensitive Memories
Buffering Systems for Accessing Multiple Layers of Memory in Integrated Circuits
Programmable Logic Device Structure Using Third Dimensional Memory
Buffering Systems Methods for Accessing Multiple Layers of Memory in Integrated Circuits
Securing Data in Memory Device
Non-Volatile Register Having a Memory Element and Register Logic Vertically Configured on a Substrate
Integrated Circuits to Control Access to Multiple Layers of Memory
Integrated circuits and methods to control access to multiple layers of memory
Method for Sensing a Signal in a Two-Terminal Memory Array Having Leakage Current
Method for Two-Cycle Sensing in a Two-Terminal Memory Array Having Leakage Current
Data Retention Structure for Non-Volatile Memory
Method for Fabricating Multi-Resistive State Memory Devices
Preservation Circuit and Methods to Maintain Values Representing Data in One or More Layers of Memory
Selection Device for Re-Writable Memory
Conductive oxide electrodes
Application:
61/203,153 →
Memory cell with band gap control
Application:
61/203,154 →
Memory stack cladding
Application:
61/203,158 →
Modulated oxide structure in a non-volatile re-writeable memory device
Application:
61/203,160 →
Conductive metal oxide structures in non-volatile re-writable memory devices
Application:
61/203,163 →
Protecting integrity of data in multi-layered memory with data redundancy
Application:
61/203,166 →
Cooperative modification of conductivity for oxide structures in non-volatile re-writable memory cells
Application:
61/203,184 →
Device fabrication
Application:
61/203,187 →
Array operation using a schottky diode as a non-ohmic isolation device
Application:
61/203,189 →
Third dimensional memory with compress engine
Application:
61/203,190 →
Memory access circuits and layout of the same for cross-point memory arrays
Application:
61/203,191 →
Configurable memory interface to provide serial and parallel access to memories
Application:
61/203,203 →
Signal margin improvement in a cross-point memory array
Application:
61/203,212 →
High voltage switching circuitry for a cross point array
Application:
61/203,229 →
Multi-structured memory
Application:
61/203,430 →
Data storage system with non-volatile memory using both page write and block program and block erase
Application:
61/203,440 →
Digital potentiometer using third dimensional memory
Application:
61/203,446 →
Memory scrubbing in third dimension memory
Application:
61/203,456 →
Actuator
Application:
61/203,912 →
Multiple layers of memory implemented as different memory technology
Application:
61/206,395 →
Data storage system with refresh in place
Application:
61/206,397 →
Fuse elements based on two-terminal re-writeable non-volatile memory
Application:
61/206,446 →
Non-volatile dual port third dimensional memory
Application:
61/206,447 →
Non-volatile FIFO with third dimension memory
Application:
61/208,933 →
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.