Conductive memory stack with sidewall
View Patent ↗A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.
1. A conductive memory device comprising:
a bottom electrode including a top face;
a top electrode located above the bottom electrode and including a bottom face having a second surface area; and
a multi-resistive state element sandwiched between the bottom electrode and the top electrode and including a bottom face and a top face, the top face having a fourth surface area, the second surface area is smaller than the fourth surface area,
the multi-resistive state element's bottom face being in contact with the bottom electrode's top face, the multi-resistive state element's top face being in contact with the top electrode's bottom face,
wherein the bottom electrode, the top electrode and the multi-resistive state element each have sides that are adjacent to their faces, and
wherein the sides are at least partially covered by a sidewall layer.
2. The conductive memory device of claim 1 , wherein the multi-resistive state element comprises a conductive metal oxide (CMO).
3. The conductive memory device of claim 2 , wherein the CMO comprises a perovskite.
4. The conductive memory device of claim 1 , wherein the multi-resistive state element comprises a two-terminal memory element.
5. The conductive memory device of claim 4 , wherein the two-terminal memory element is configured in a cross point memory array including at least one layer of memory.
6. A conductive memory device comprising:
a bottom electrode including a top face;
a top electrode located above the bottom electrode and including a bottom face having a second surface area;
a hard mask layer including a bottom face with a surface area substantially similar to the second surface area, the top electrode including a top face that is in contact with the bottom face of the hard mask layer; and
a multi-resistive state element sandwiched between the bottom electrode and the top electrode and including a bottom face and a top face, the top face having a fourth surface area, the second surface area is smaller than the fourth surface area,
the multi-resistive state element's bottom face being in contact with the bottom electrode's top face, the multi-resistive state element's top face being in contact with the top electrode's bottom face,
wherein the bottom electrode, the top electrode and the multi-resistive state element each have sides that are adjacent to their faces, and
wherein the sides are at least partially covered by a sidewall layer.
7. The conductive memory device of claim 6 , wherein the multi-resistive state element comprises a conductive metal oxide (CMO).
8. The conductive memory device of claim 7 , wherein the CMO comprises a perovskite.
9. The conductive memory device of claim 6 , wherein the multi-resistive state element comprises a two-terminal memory element.
10. The conductive memory device of claim 9 , wherein the two-terminal memory element is configured in a cross point memory array including at least one layer of memory.
11. A conductive memory device comprising:
a bottom electrode including a top face;
a top electrode located above the bottom electrode and including a bottom face; and
a multi-resistive state element sandwiched between the bottom electrode and the top electrode and including a bottom face and a top face, the multi-resistive state element's bottom face being in contact with the bottom electrode's top face, and the multi-resistive state element's top face being in contact with the top electrode's bottom face,
the bottom electrode's top face has a first surface area, the top electrode's bottom face has a second surface area, the multi-resistive state element's bottom face has a third surface area, the multi-resistive state element's top face has a fourth surface area, the first second, third and fourth surface areas are approximately equal,
the bottom electrode's top face, the top electrodes bottom face, the multi-resistive state element's bottom face, and the multi-resistive state element's top face are substantially aligned, thereby all the faces have the same footprint,
wherein the bottom electrode, the top electrode and the multi-resistive state element each have sides that are adjacent to their faces and the sides are at least partially covered by a sidewall layer, and
wherein the multi-resistive state element comprises a two-terminal memory element configured in a cross point memory array including at least one layer of memory.