Cross point memory array with memory plugs exhibiting a characteristic hysteresis
View Patent ↗Providing a cross point, memory array with memory plugs exhibiting a characteristic hysteresis. The memory plugs exhibit a hysteresis that, in the low resistive state, the first write threshold voltage is the point above which any voltages applied across the memory plug have substantially no effect on the resistive state and below which a voltage pulse will alter the resistance of the memory plug. Similarly, in the high resistive state, the second write threshold voltage is the point below which any voltages applied across the memory plug have substantially no effect on the resistive state and above which a voltage pulse will alter the resistance of the memory plug. The read voltages applied to the memory plug are typically above the first write threshold voltage and lower than the second write threshold voltage.
1. A cross point memory array comprising:
a first layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with each other;
a second layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with either each other or any of the conductive array lines of the first layer;
a plurality of memory plugs located at the intersections of the first layer of conductive array lines and the second layer of conductive array lines, each memory plug
being in electrical contact with one of the conductive array lines from the first layer and one of the conductive array lines from the second layer such that each memory plug is associated with a unique pair of conductive array lines;
having a low resistive state and a high resistive state, the resistive state of the memory plug capable of being determined when a read voltage is applied across the unique pair of conductive array lines; and
exhibiting a hysteresis that is characterized by a first write threshold when the memory plug is in the low resistive state and a second state threshold when the memory plug is in the high resistive state, wherein
voltages applied across the unique pair of conductive array lines that are higher than the first write threshold have substantially no effect on the resistive state of the memory plug when the memory plug is in the low resistive state; and
voltages applied across the unique pair of conductive array lines that are lower than the second write threshold voltage have substantially no effect on the resistive state of the memory plug when the memory plug is in the high resistive state.
2. The cross point memory array of claim 1 , wherein the read voltage is higher than the first write threshold voltage and lower than the second write threshold voltage.
3. The cross point memory array of claim 1 , wherein voltage pulse applied across the unique pair of conductive array lines that is suitable to change the memory plug from a low resistive state to a high resistive state can change the resistive state of the memory plug in less than 50 nanoseconds.
4. The cross point memory array of claim 1 , wherein a voltage pulse applied across the unique par of conductive array lines that is suitable to change the memory plug from a high resistive state to a low resistive state can change the resistive state of the memory plug in less than 50 nanoseconds.
5. The cross point memory array of claim 1 , wherein repeated application of the read voltage over ten years will not change the resistive state of the memory plug.
6. The cross point memory array of claim 1 , wherein the resistive state will be maintained for a minimum of ten years if no voltage is applied across the unique pair of conductive array lines that is lower than the first write threshold or higher than the second write threshold.
7. A method comprising:
selecting a unique pair of conductive array lines associated with the single memory plug, the unique pair consisting of a first layer conductive array line and a second layer conductive array line, wherein the memory plug exhibits a hysteresis that is characterized by
a first write threshold voltage, above which voltages applied across the unique pair of conductive array lines have substantially no effect on the resistive state of the memory plug when the memory plug is in the low resistive state; and
a second write threshold voltage, below which voltages applied across the unique pair of conductive array lines have substantially no effect on the resistive state of the memory plug when the memory plug is in the high resistive state.
8. The method of claim 7 , further comprising applying a read voltage across the unique pair of conductive array lines, wherein the read voltage is above the first write threshold voltage and lower than the second write threshold voltage.
9. A cross point memory array comprising:
a first layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with each other;
a second layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with either each other or any of the conductive array lines of the first layer;
a plurality of memory plugs located at the intersections of the first layer of conductive array lines and the second layer of conductive array lines, each memory plug
being in electrical contact with one of the conductive array lines from the first layer and one of the conductive array lines from the second layer such that each memory plug is associated with a unique pair of conductive array lines:
having a low resistive state and a high resistive state, the resistive state of the memory plug capable of being determined when a read voltage is applied across the unique pair of conductive array lines; and
exhibiting a hysteresis that is characterized by a first write threshold when the memory plug is in the low resistive state and a second write threshold when the memory plug is in the high resistive state, wherein
voltages applied across the unique pair of conductive array lines that are lower than the first write threshold have substantially no effect on the resistive state of the memory plug when the memory plug is in the low resistive state; and
voltages applied across the unique pair of conductive array lines that are higher than the second write threshold voltage have substantially no effect on the resistive state of the memory plug when the memory plug is in the high resistive state.
10. The cross point memory array of claim 9 , wherein the read voltage is lower than the first write threshold voltage and higher than the second write threshold voltage.
11. The cross point memory array of claim 9 , wherein a voltage pulse applied across the unique pair of conductive array lines that is suitable to change the memory plug from a low resistive state to a high resistive state can change the resistive state of the memory plug in less than 50 nanoseconds.
12. The cross point memory array of claim 9 , wherein a voltage pulse applied across the unique pair of conductive array lines that is suitable to change the memory plug from a high resistive state to a low resistive state can change the resistive state of the memory plug in less than 50 nanoseconds.
13. The cross point memory array of claim 9 , wherein repeated application of the read voltage over ten years will not change the resistive state of the memory plug.
14. The cross point memory array of claim 9 , wherein the resistive state will be maintained for a minimum of ten years if no voltage is applied across the unique pair of conductive array lines that is higher than the first write threshold or lower than the second write threshold.
15. A method comprising:
selecting a unique pair of conductive array lines associated with the single memory plug, the unique pair consisting of a first layer conductive array line and a second layer conductive array line, wherein the memory plug exhibits a hysteresis that is characterized by
a first write threshold voltage, below which voltages applied across the unique pair of conductive array lines have substantially no effect on the resistive state of the memory plug when the memory plug is in the low resistive state, and
a second write threshold voltage, above which voltages applied across the unique pair of conductive array lines have substantially no effect on the resistive state of the memory plug when the memory plug is in the high resistive state.
16. The method of claim 15 , further comprising applying a read voltage across the unique pair of conductive array lines, wherein the read voltage is lower than the first write threshold voltage and higher than the second write threshold voltage.