IP Library Granted Patent US 7,439,082
Granted Patent B2
US 7,439,082 · App. 11/369,663 · Granted Oct 21, 2008

Conductive memory stack with non-uniform width

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Quick Facts
Patent No.
US 7,439,082
App. No.
11/369,663
Granted
Oct 21, 2008
Kind
B2
Abstract

A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has a bottom face with a second surface area and the multi-resistive state element has a bottom face with a third surface area and a top face with a fourth surface area. The multi-resistive state element's bottom face is in contact with the bottom electrode's top face and the multi-resistive state element's top face is in contact with the top electrode's bottom face. Furthermore, the fourth surface area is not equal to the second surface area.

Claims (12)

1. A method of making a plurality of conductive memory devices, each conductive memory device operable to be reversibly placed in multiple resistive states, the method comprising:

sputtering a bottom electrode layer;

sputtering a multi-resistive state element layer, the multi-resistive state element layer including a conductive perovskite;

sputtering a top electrode layer;

depositing a hard mask layer;

photo lithographically patterning the hard mask layer and the top electrode layer such that the patterned top electrode and hard mask have a first cross sectional area;

depositing a dielectric material;

etching the dielectric anisotropically to create a sidewall spacer at the edges of the top electrode;

etching the multi-resistive state element layer and the bottom electrode layer using the hard mask such that the etched bottom electrode and multi-resistive state element have a second cross sectional area that is larger than the first cross sectional area; and

wet etching the multi-resistive state element layer,

wherein the wet etching is performed after the etching of the multi-resistive state element layer, the etching of the multi-resistive state element layer forming multi-resistive state element sides, and

wherein the wet etching of the multi-resistive state element removes a thickness of 50-150 Å, thereby forming an undercut from the multi-resistive state element sides.

Assignments (5)
RELEASE Recorded Apr 9, 2012
From: SILICON VALLEY BANK; GOLD HILL CAPITAL
To: UNITY SEMICONDUCTOR, INC.
Reel/Frame 028132/0675 →
SECURITY AGREEMENT Recorded Apr 13, 2009
From: UNITY SEMICONDUCTOR CORPORATION
To: GOLD HILL CAPITAL
Reel/Frame 023129/0669 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ORIGINAL COVERSHEET FOR APPLICATION 11473005 ERRONEOUSLY ATTACHED TO CORRECTIVE ASSIGNMENT FOR APPLICATION 11369663 FILED 7/1/08 PREVIOUSLY RECORDED ON REEL 021181 FRAME 0105. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.. Recorded Oct 20, 2008
From: RINERSON, DARRELL, MR.; HSIA, STEVE KUO-REN; LONGCOR, STEVEN W.
To: UNITY SEMICONDUCTOR CORPORATION
Reel/Frame 021710/0308 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CHRISTOPHE J. CHEVALLIER TO BE DELETED AS AN INVENTOR. STEVE KUO-REN HSIA TO BE ADDED AS AN INVENTOR AND ASSIGNOR. PREVIOUSLY RECORDED ON REEL 020250 FRAME 0628. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 1, 2008
From: RINERSON, DARRELL, MR.; HSIA, STEVE KUO-REN, MR.; LONGCOR, STEVEN W., MR.
To: UNITY SEMICONDUCTOR CORPORATION
Reel/Frame 021181/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2007
From: RINERSON, DARRELL, MR.; CHEVALLIER, CHRISTOPHE, MR.; LONGCOR, STEVEN
To: UNITY SEMICONDUCTOR CORPORATION
Reel/Frame 020250/0628 →