Field programmable gate arrays using resistivity sensitive memories
View Patent ↗Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.
1. A programmable cell comprising:
a configurable logic;
a memory connected with the configurable logic an operative to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element;
an input/output logic connected with the configurable logic and the memory and configured to communicate with other programmable cells;
a sequencer connected with the memory and operative to provide addresses to the memory; and
an interface connected with the memory and operative to provide write data to the memory.
2. A programmable cell comprising:
a memory connected with the configurable logic an operative to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element;
an input/output logic connected with the configurable logic and the memory and configured to communicate with other programmable cells,
wherein the configurable logic and the input/output logic are in a first plane of an integrated circuit, wherein the memory is in at least a second plane of the integrated circuit and the second plane is vertically configured above the first plane; and
a second memory connected with the memory, the second memory comprises an internal memory for the programmable cell, and
wherein the second memory comprises a boot memory for the programmable cell.
3. A programmable cell comprising:
a configurable logic;
a memory connected with the configurable logic an operative to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element;
an input/output logic connected with the configurable logic and the memory and configured to communicate with other programmable cells,
wherein the configurable logic and the input/output logic are in a first plane of an integrated circuit, wherein the memory is in at least a second plane of the integrated circuit and the second plane is vertically configured above the first plane; and
a memory logic in the first plane connected with the memory and operative to control the memory.
4. A programmable cell comprising:
a configurable logic;
a first memory connected with the configurable logic and operative to provide data for the configurable logic; and
a second memory connected with the first memory and operative to provide the data to the first memory during booting, the second memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element,
wherein the first memory comprises a second non-volatile rewriteable memory element including a second resistivity-sensitive memory element.
5. A programmable cell comprising:
a configurable logic;
a first memory connected with the configurable logic and operative to provide data for the configurable logic;
a second memory connected with the first memory and operative to provide the data to the first memory during booting, the second memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element;
an input/output logic connected with the configurable logic and the first memory and operative to communicate with other programmable cells; and
a switch connected with the input/output logic and operative to direct communications between the programmable cell and the other programmable cells.
6. A programmable cell comprising:
a configurable logic;
a first memory connected with the configurable logic and operative to provide data for the configurable logic;
a second memory connected with the first memory and operative to provide the data to the first memory during booting, the second memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element;
an input/output logic connected with the configurable logic and the first memory and operative to communicate with other programmable cells; and
a switch connected with the input/output logic and operative to direct communications between the programmable cell and the other programmable cells,
wherein the switch includes a register, the register including a third non-volatile rewritable resistivity-sensitive memory element.
7. A programmable cell comprising:
a configurable logic;
a first memo connected with the configurable logic and operative to provide data for the configurable logic;
a second memory connected with the first memory and operative to provide the data to the first memory during booting, the second memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element;
an input/output logic connected with the configurable logic and the first memory and operative to communicate with other programmable cells; and
a switch connected with the input/output logic and operative to direct communications between the programmable cell and the other programmable cells,
wherein the configurable logic is in a first plane of an integrated circuit, wherein the second memory is in a second plane of the integrated circuit and the second plane is vertically configured above the first plane.
8. A programmable cell comprising:
a configurable logic;
a first memory connected with the configurable logic and operative to provide data for the configurable logic;
a second memory connected with the first memory and operative to provide the data to the first memory during booting, the second memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element;
an input/output logic connected with the configurable logic and the first memory and operative to communicate with other programmable cells; and
a switch connected with the input/output logic and operative to direct communications between the programmable cell and the other programmable cells,
wherein the configurable logic is in a first plane of an integrated circuit, wherein the second memory is in a second plane of the integrated circuit and the second plane is vertically configured above the first plane, and
wherein the first memory is in the first plane.
9. A programmable cell comprising:
a configurable logic;
a first memory connected with the configurable logic and operative to provide data for the configurable logic;
a second memory connected with the first memory and operative to provide the data to the first memory during booting, the second memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element;
an input/output logic connected with the configurable logic and the first memory and operative to communicate with other programmable cells; and
a switch connected with the input/output logic and operative to direct communications between the programmable cell and the other programmable cells,
wherein the configurable logic is in a first plane of an integrated circuit, wherein the second memory is in a second plane of the integrated circuit and the second plane is vertically configured above the first plane, and
wherein the first memory is in the second plane.
10. A field programmable gate array comprising:
a programmable cell comprising a configurable logic and a first memory connected with the configurable logic, the first memory operative to provide functions for the configurable logic;
a second memory connected with the programmable cell, the second memory operative to boot the first memory and to provide the functions to the first memory, the second memory comprises a non-volatile memory including a resistivity-sensitive memory element;
an interface connected with the second memory and the programmable cell and operative to provide write data to the second memory; and
a sequencer operative to provide addresses to the second memory.
11. The field programmable gate array of claim 10 , wherein the first memory comprises a second non-volatile memory including a second resistivity-sensitive memory element.
12. The field programmable gate array of claim 11 ,
wherein the configurable logic, the interface, and the sequencer are in a first plane of an integrated circuit,
wherein the first memory and the second memory are in a second plane of the integrated circuit and the second planes is vertically configured above the first plane.
13. The field programmable gate array of claim 10 ,
wherein the configurable logic, the interface, the sequencer, and the first memory are in a first plane of an integrated circuit,
wherein the second memory is in a second plane of the integrated circuit and the second plane is vertically configured above the first plane.
14. The programmable cell of claim 10 , wherein the resistivity-sensitive memory element comprises a two-terminal resistivity-sensitive memory element.
15. A field programmable gate array comprising:
a programmable cell including a configurable logic and a memory connected with the configurable logic, the memory operative to provide functions for the configurable logic, the memory comprises a non-volatile memory including a resistivity-sensitive memory element;
an interface connected with the memory and the programmable cell and operative to provide write data to the memory; and
a switch connected with the programmable cell and operative to direct communications between the programmable cell and other programmable cells, wherein the programmable cell further comprises an input/output logic connected with the configurable logic, the memory, and the switch, and the input/output logic operative to communicate with the other programmable cells.
16. A field programmable gate array comprising:
a programmable cell including a configurable logic and a memory connected with the configurable logic, the memory operative to provide functions for the configurable logic, the memory comprises a non-volatile memory including a resistivity-sensitive memory element;
an interface connected with the memory and the programmable cell and operative to provide write data to the memory; end
a second memory connected with the programmable cell and operative to provide an internal memory for the programmable cell; wherein the second memory comprises a second non-volatile rewritable memory including a second resistivity-sensitive memory element.