Emulation of a NAND memory system
View Patent ↗A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example.
1. A memory system, comprising:
a vertically configured non-volatile memory array including at least one memory plane in contact with a substrate and positioned above circuitry fabricated in a logic plane of the substrate;
an input/output controller connected with the vertically configured non-volatile memory array; and
a memory controller connected with the vertically configured non-volatile memory array and the input/output controller, the memory controller being configured to interface with a command associated with a NAND memory and being configured to access the vertically configured non-volatile memory array based on the command.
2. The memory system of claim 1 , wherein the memory controller includes logic configured to,
receive a block erase command to erase a memory block,
assert a busy signal for a time period, and
release the busy signal after the time period,
wherein an erase operation is not performed during the time period.
3. The memory system of claim 1 , wherein the memory controller includes logic configured to,
receive a block erase command to erase a memory block,
assert a busy signal,
write a plurality of zeros to the memory block, and
release the busy signal after writing the plurality of zeros to the memory block.
4. The memory system of claim 3 , wherein the logic configured to write the plurality of zeros to the memory block includes logic configured to write the plurality of zeros to an overhead section and a data section associated with the memory block.
5. The memory system of claim 3 , wherein the logic configured to write the plurality of zeros to the memory block includes logic configured to write the plurality of zeros to a data section associated with the memory block.
6. The memory system of claim 3 , wherein the logic configured to write the plurality of zeros to the memory block includes logic configured to write the plurality of zeros to an overhead section associated with the memory block.
7. The memory system of claim 3 , wherein the input/output controller includes logic configured to receive a plurality of data and a memory address associated with the plurality of data,
wherein the memory controller includes logic configured to receive a write command, to write the plurality of data to the memory address based on the write command, and to write the plurality of data to the vertically configured non-volatile memory array at the memory address,
wherein the plurality of data is written to the vertically configured non-volatile memory array without performing an erase operation before writing the plurality of data to the vertically configured non-volatile memory array.
8. The memory system of claim 1 , wherein the vertically configured non-volatile memory array is divided into a plurality of memory blocks.
9. The memory system of claim 8 , wherein each of the plurality of memory blocks is divided into a plurality of pages.
10. The memory system of claim 1 , wherein the vertically configured non-volatile memory array includes a plurality of two-terminal memory cells.
11. The memory system of claim 1 , wherein the vertically configured non-volatile memory array is configured as a cross-point array.
12. A memory system, comprising:
an input/output controller; and
a memory controller connected with the input/output controller, the memory controller being configured to
receive a block erase command associated with a NAND memory,
assert a busy signal for a time period, and
release the busy signal after the time period,
wherein an erase operation is not performed during the time period.
13. The memory system of claim 12 , wherein the memory controller is further configured to write a plurality of zeros to a memory block during the time period.
14. The memory system of claim 13 , wherein the plurality of zeros is written to an overhead section and a data section associated with the memory block.
15. The memory system of claim 13 , wherein the plurality of zeros is written to a data section associated with the memory block without writing the plurality of zeros to an overhead section associated with the memory block.
16. The memory system of claim 12 and further comprising:
a vertically configured non-volatile memory array connected with the input/output controller and the memory controller.
17. The memory system of claim 16 , wherein the vertically configured non-volatile memory is divided into a sector, the sector including an overhead section and a data section.
18. The memory system of claim 16 , wherein the vertically configured non-volatile memory array includes a plurality of two-terminal memory cells.
19. The memory system of claim 16 , wherein the vertically configured non-volatile memory array is configured as a cross-point array.
20. A method for emulating a NAND memory system, comprising:
receiving a command associated with a NAND memory; and
accessing a vertically configured non-volatile memory array based on the command associated with the NAND memory, the vertically configured non-volatile memory array including at least one memory plane in contact with a substrate and positioned above circuitry fabricated in a logic plane of the substrate.
21. The method of claim 20 , wherein the command associated with the NAND memory is a block erase command to erase a memory block and wherein the accessing the vertically configured non-volatile memory array comprises,
asserting a busy signal for a time period, and
releasing the busy signal after the time period,
wherein an erase operation is not performed during the time period.
22. The method of claim 20 , wherein the command associated with the NAND memory is a block erase command to erase a memory block and wherein the accessing the vertically configured non-volatile memory array comprises,
asserting a busy signal,
writing a plurality of zeros to the memory block, and
releasing the busy signal after the writing of the plurality of zeros to the memory block.
23. The method of claim 20 , wherein the command associated with the NAND memory is a write command to write a plurality of data and wherein the accessing the vertically configured non-volatile memory array comprises writing the plurality of data to the vertically configured non-volatile memory array without performing an erase operation before the writing of the plurality of data.
24. The method of claim 20 , wherein the vertically configured non-volatile memory array is divided into a plurality of memory blocks, each of the plurality of memory blocks being divided into a plurality of pages.
25. The method of claim 20 , wherein the vertically configured non-volatile memory array includes a plurality of two-terminal memory cells.