IP Library Granted Patent US 7,063,984
Granted Patent B2
US 7,063,984 · App. 10/387,773 · Granted Jun 20, 2006

Low temperature deposition of complex metal oxides (CMO) memory materials for non-volatile memory integrated circuits

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Quick Facts
Patent No.
US 7,063,984
App. No.
10/387,773
Granted
Jun 20, 2006
Kind
B2
Abstract

A memory fabrication apparatus includes a pair of targets arranged so as to be spaced apart from one another within a closed vacuum vessel, each target of said pair of targets having a sputtering surface facing the sputtering surface of the other target of said pair of targets; and substrate holder adapted to receive facing target sputtering a CMO material on an electrode.

Claims (47)

1. A memory fabrication apparatus comprising:

a. a pair of targets arranged so as to be spaced apart from one another within a closed vacuum vessel, each target of said pair of targets having a sputtering surface facing the sputtering surface of the other target of said pair of targets; and

b. a substrate holder adapted to receive facing target sputtering a complex metal oxide (CMO) material on an electrode wherein the CMO material is adapted to operate within a cross point memory array and the CMO material is deposited on circuitry.

2. The apparatus of claim 1 , wherein the CMO material comprises a manganite, titanate or zirconate.

3. The apparatus of claim 1 , wherein the CMO material is a perovskite.

4. The apparatus of claim 1 , wherein the CMO material is a non-perovskite.

5. The apparatus of claim 4 , wherein the CMO material is deposited at a temperature above 350° C.

6. The apparatus of claim 5 , wherein the CMO material is deposited at a temperature below 550° C.

7. The apparatus of claim 1 , wherein the electrode comprises a metal or a conductive metal oxide.

8. The apparatus of claim 1 , wherein the electrode comprises a diffusion barrier.

9. The apparatus of claim 1 , wherein the electrode comprises a plug.

10. The apparatus of claim 1 , wherein the CMO material is adapted to operate within an array of memory cells capable of storing at least a Megabit of information, each memory cell including a memory plug that includes a memory element that switches from a first resistance state to a second resistance state upon application of a first write voltage of a first polarity and reversibly switches from the second resistance state to the first resistance state upon application of a second write voltage of polarity opposite to the first polarity.

11. The apparatus of claim 1 , wherein the CMO material is crystalline.

12. The apparatus of claim 1 , wherein the CMO material is a polycrystalline structure, wherein the polycrystalline structure comprises a small grain size.

13. The apparatus of claim 12 , wherein the small grain size is approximately 0.1 micron or less.

14. The apparatus of claim 1 , wherein the CMO material comprises a conductive metal oxide material on the electrode.

15. The apparatus of claim 1 , wherein the CMO material comprises a manganite.

16. The apparatus of claim 1 , wherein the CMO material comprises a titanate.

17. The apparatus of claim 1 , wherein the CMO material comprises a zirconate.

18. The apparatus of claim 1 , wherein the vacuum vessel comprises an ambient environment for annealing.

19. The apparatus of claim 18 , wherein the ambient environment comprises nitrogen.

20. The apparatus of claim 18 , wherein the ambient environment comprises argon.

21. A memory fabrication apparatus, comprising:

a. a pair of targets arranged so as to be spaced apart from one another within a closed vacuum vessel, each target of said pair of targets having a sputtering surface facing the sputtering surface of the other target of said pair of targets; and

b. a substrate holder adapted to receive facing target sputtering a complex metal oxide (CMO) material on an electrode;

wherein a memory resulting from the memory fabrication apparatus switches from a first resistance state to a second resistance state upon application of a first write voltage of a first polarity and reversibly switches from the second resistance state to the first resistance state upon application of a second write voltage of polarity opposite to the first polarity, wherein the CMO material is deposited on circuitry.

22. A semiconductor fabrication process, comprising:

a. providing at least a pair of facing targets arranged so as to be spaced apart from one another within a closed vacuum vessel, each target of said pair of targets having a sputtering surface facing the sputtering surface of the other target of said pair of targets; and

b. sputtering a CMO memory material on an eletrode, wherein the CMO memory material is adapted to operate within a cross point memory array and the CMO memory material is deposited on circuitry.

23. The process of claim 22 , wherein the electrode comprises a metal or a conductive metal oxide.

24. The process of claim 22 , wherein the electrode comprises a diffusion barrier.

25. The process of claim 22 , the electrode comprises a plug.

26. The process of claim 22 , wherein the CMO memory material comprises a manganite, a titanate or a zirconate.

27. The process of claim 22 , wherein the CMO material is a perovskite.

28. The process of claim 22 , wherein the CMO material is a non-perovskite.

29. The process of claim 22 , wherein the CMO material is deposited at a temperature below 375° C.

30. The process of claim 22 , wherein the CMO material comprises a polycrystalline structure.

31. A semiconductor fabrication process, comprising:

a. providing a pair of targets arranged so as to be spaced apart from one another within a closed vacuum vessel, each target of said pair of targets having a sputtering surface facing the sputtering surface of the other target of said pair of targets;

b. applying an electric power to said pair of targets to cause sputtering from the sputtering surface of each target of said pair of targets;

c. generating at least a perpendicular magnetic field extending in a direction perpendicular to said sputtering surfaces to confine plasma-in a space between said sputtering surfaces; and

d. face target sputtering a CMO memory material on an eletrode, wherein the CMO memory material is adapted to operation within a cross point memory array and the CMO memory material is deposited on circuitry.

32. The process of claim 31 , wherein the CMO memory material comprises a polycrystalline structure.

33. The process of claim 32 , wherein the CMO memory material comprises a manganite.

34. The process of claim 32 , wherein the CMO memory material comprises a rare earth metal and an alkaline earth metal.

35. The process of claim 32 , wherein the CMO memory material comprises a zirconate.

36. The process of claim 32 , wherein the CMO memory material comprises a titanate.

Assignments (3)
RELEASE Recorded Apr 9, 2012
From: SILICON VALLEY BANK; GOLD HILL CAPITAL
To: UNITY SEMICONDUCTOR, INC.
Reel/Frame 028132/0675 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRESPONDENCE INFORMATION AND REMOVE THE DOMESTIC REPRESENTATIVE INFORMATION PREVIOUSLY RECORDED ON REEL 013870 FRAME 0203. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 24, 2009
From: NAGASHIMA, MAKOTO; RINERSON, DARRELL; HSIA, STEVE K; MATHENY, LARRY
To: UNITY SEMICONDUCTOR CORPORATION
Reel/Frame 022871/0951 →
SECURITY AGREEMENT Recorded Apr 13, 2009
From: UNITY SEMICONDUCTOR CORPORATION
To: GOLD HILL CAPITAL
Reel/Frame 023129/0669 →