Memory element having islands
View Patent ↗A memory including a memory element having islands is provided. The memory has address decoding circuitry and an array of memory plugs. The memory plugs include memory element that have island structures of a first material within the bulk of a second material. The island structures are typically nanoparticles. The memory plugs can be placed in a first resistive state at a first write voltage, placed in a second resistive state at a second write voltage, and have its resistive state determined at a read voltage.
1. A memory comprising:
address lines operable to carry addresses;
control lines operable to carry control signals;
data lines operable to carry data;
array lines;
an address decoder that decodes the address on the address lines and activates certain array lines;
drivers that, as a function of the control signals, can cause some array lines to be placed at a first write voltage, a second write voltage, or a read voltage;
two-terminal memory plugs, each two-terminal memory plug electrically connected to at least one array line, the two-terminal memory plug being able to be reversibly written to a first resistive state when the some array lines are at the first write voltage, reversibly written to a second resistive state when the some array lines are at the second write voltage, and have its resistive state undisturbed when the some array lines are at the read voltage;
wherein the two-terminal memory plugs include memory elements that have island structures of a first material within the bulk of a second material.
2. The memory of claim 1 , wherein the first material is more conductive than the second material.
3. The memory of claim 2 , wherein second material is a semiconductor.
4. The memory of claim 3 , wherein the second material is a perovskite.
5. The memory of claim 4 , wherein the first material is formed through deposition of a reactive metal in middle of the perovskite.
6. The memory of claim 2 , wherein the first material is a non-reactive metal.
7. The memory of claim 2 , wherein the first material is separated from the bulk of the second material by an insulating envelope.
8. The memory of claim 1 , wherein the two-terminal memory plug includes electrodes at each terminal.
9. The memory of claim 8 , wherein the electrodes are formed in parallel planes and the islands are formed in a plane that is parallel the planes of the electrodes.
10. The memory of claim 1 , wherein the islands are between 0.5 and 50 nanometers thick.
11. The memory of claim 1 , wherein a transistor is interposed between each of the two-terminal memory plugs and the at least one array line that it is electrically connected to.
12. The memory of claim 1 , wherein each of the two-terminal memory plug is in electrical contact with exactly two array lines such that each terminal is connected to one array line.
13. A memory comprising:
address lines;
address decoding circuitry in communication with the address lines; and
addressable two-terminal memory plugs that are activated by the address decoding circuitry, each two-terminal memory plug including
a pair of electrodes, each electrode defining a terminal; and
nanoparticles of a first material embedded within the bulk of a second material,
the bulk of the second material being in electrical communication with the electrodes;
wherein, when the addressable two-terminal memory plug is activated, the addressable two-terminal memory plug can be reversibly written to a first resistive state at a fist write voltage, reversibly written to a second resistive state at a second write voltage, and have its resistive state determined at a read voltage.