Fast data access through page manipulation
View Patent ↗A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and, when the page buffer module is full with aligned data, transferring the aligned data to the memory. The method includes receiving data at an interface, aligning the data to generate aligned data, storing aligned data in a page buffer module configured to store aligned data for a write access and retrieved data from a read access, writing aligned data to a memory, and transferring retrieved data to the interface. Data can be transferred by the interface at a first rate and aligned data can be written to or retrieved from the memory at substantially the first rate.
1. A memory system, comprising:
a memory;
a page buffer module configured to receive aligned data and to output the aligned data to a block of addresses in the memory;
an interface operable to receive a data packet, the data packet including a plurality of formatted data fields including at least a data operation access type data field, an end of frame (EOF) data field, a cyclic redundancy check (CRC) data field, and at least one synchronization (Sync) data field; and
an aligner configured to receive the data packet from the interface and operative to align data included in the data packet based on data included in one or more of the plurality of formatted data fields, and to generate aligned data with a starting address anywhere within the block of addresses, the starting address determined by at least one of the plurality of formatted data fields.
2. The memory system of claim 1 , wherein one or more of the plurality of formatted data fields includes alignment information that is used by the aligner to generate the aligned data.
3. The memory system of claim 1 , wherein the interface comprises at least one serial interface.
4. The memory system of claim 1 , wherein the interface comprises at least one parallel interface.
5. The memory system of claim 1 , wherein the interface comprises at least one high speed serial interface.
6. The memory system of claim 1 , wherein the interface receives the data packet at a first rate and the page buffer module temporarily stores the aligned data before transferring the aligned data to the memory at the first rate.
7. The memory system of claim 6 , wherein the aligner aligns data through byte shifting.
8. The memory system of claim 6 , wherein the aligner is configured to transfer the aligned data to the page buffer module at the first rate.
9. The memory system of claim 1 and further comprising: a second aligner configured to receive data from a block of addresses in the memory, to align the data, to generate aligned data corresponding to a second starting address within the block of addresses, and to transmit aligned data to the interface.
10. The memory system of claim 1 , wherein the aligner is further configured to receive data from a block of addresses in the memory, to align the data, to generate aligned data corresponding to a second starting address within the block of addresses, and to transmit aligned data to the interface.
11. The memory system of claim 1 and further comprising:
a second page buffer module configured to receive aligned data from a block of address in the memory and to output the aligned data to the interface.
12. The memory system of claim 1 and further comprising:
a second aligner configured to receive the data packet from the interface, to align data included in the data packet based on data included in one or more of the plurality of formatted data fields, and to generate aligned data with a second starting address anywhere within the block of addresses, the second starting address determined by at least one of the plurality of formatted data fields.
13. The memory system of claim 1 , wherein the page buffer module includes a first page buffer and a second page buffer, the page buffer module configured to alternately fill the first and second page buffers with aligned data,
wherein when the first page buffer is full with aligned data, the aligned data is transferred to a selected one of the block of addresses in the memory during a write access or to the interface during a read access, and
wherein when the second page buffer is full of aligned data, the aligned data is transferred to a selected one of the block of addresses in the memory during a write access or to the interface during a read access.
14. The memory system of claim 13 , wherein the interface receives the data packet at a first rate and the first and second page buffers transfer their respective aligned data to the block of addresses in the memory at the first rate during the write access.
15. The memory system of claim 13 , wherein the interface is operative to transmit aligned data at a first rate and the first and second page buffers transfer their respective aligned data to the interface at the first rate.
16. The memory system of claim 1 , wherein the memory comprises a selected one of a non-volatile two-terminal cross-point memory array or a non-volatile stacked cross-point memory array.
17. A memory system, comprising:
a non-volatile memory;
a serial interface configured to transfer a data packet during data operations to the non-volatile memory, the data packet including a plurality of formatted data fields including at least a data operation access type data field, an end of frame (EOF) data field, a cyclic redundancy check (CRC) data field, and at least one synchronization (Sync) data field;
a write aligner configured to receive the data packet from the interface during a write operation, to align data included in the data packet based on data included in one or more of the plurality of formatted data fields, and to generate aligned data with a starting address anywhere within a block of addresses in the non-volatile memory, the starting address determined by at least one of the plurality of formatted data fields;
a write enable module configured to enable at least one address in the block of addresses;
a write page buffer module configured to receive aligned data from the write aligner and to output the aligned data to the block of addresses;
a read aligner configured to receive a block of data from the non-volatile memory during a read access, to align data included in the block of data, and to generate aligned data; and
a read page buffer module configured to receive the aligned data from the read aligner and to transfer the aligned data to the interface.
18. The memory system as set forth in claim 17 , wherein the interface receives the data packet at a first rate and the write page buffer module temporarily stores the aligned data before transferring the aligned data to the non-volatile memory at the first rate.
19. The memory system as set forth in claim 17 , wherein the interface transmits aligned data at a first rate and the read page buffer module temporarily stores the aligned data before transferring the aligned data to the interface at the first rate.
20. The memory system as set forth in claim 17 , wherein the non-volatile memory comprises a selected one of a two-terminal cross-point memory array or a stacked cross-point memory array.