IP Library Granted Patent US 8,062,942
Granted Patent B2
US 8,062,942 · App. 12/215,958 · Granted Nov 22, 2011

Method for fabricating multi-resistive state memory devices

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Quick Facts
Patent No.
US 8,062,942
App. No.
12/215,958
Granted
Nov 22, 2011
Kind
B2
Abstract

A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

Claims (30)

1. A method for fabricating non-volatile two-terminal memory devices, comprising:

depositing a bottom electrode;

depositing a conductive metal oxide (CMO), the CMO in contact with the bottom electrode;

depositing a reactive metal, the reactive metal is in contact with the CMO and the reactive metal reacts with the CMO; and

depositing a top electrode, the top electrode in contact with the reactive metal, and

the depositing of the CMO and the reactive metal forming a two-terminal memory element that is reversibly programmable to different resistive states and the resistive states are retained in the absence of electrical power, the memory element including a first non-linear I-V characteristic for all values of the resistive states, and the memory element is electrically in series with its respective top and bottom electrodes.

2. The method as set forth in claim 1 , wherein the reactive metal is Al, Ti, Mg, W, Fe, Cr, Vn, Zn, Ta, or Mo.

3. The method as set forth in claim 1 , wherein at least one of the electrodes is Pt.

4. The method as set forth in claim 1 and further comprising:

annealing the reactive metal.

5. The method as set forth in claim 4 , wherein the annealing of the reactive metal occurs in a non-reactive ambient.

6. The method as set forth in claim 1 , wherein the depositing of the reactive metal results in a very thin layer of material that is less than 200 Angstroms thick.

7. The method as set forth in claim 6 , wherein the very thin layer of material is less than 100 Angstroms thick.

8. The method as set forth in claim 1 , wherein the depositing of the reactive metal occurs prior to the depositing of the CMO.

9. The method as set forth in claim 1 , wherein the depositing of the reactive metal occurs after the depositing of the CMO.

10. The method as set forth in claim 1 , wherein the CMO comprises a perovskite.

11. The method as set forth in claim 1 and further comprising:

removing an unreacted portion of the reactive metal.

12. The method as set forth in claim 1 and further comprising:

providing a semiconductor substrate including active circuitry fabricated front-end-of-the line (FEOL) on the semiconductor substrate, and

wherein the depositing occurs after the providing so that the memory elements are fabricated directly above the active circuitry after completion of the FEOL fabrication.

13. The method as set forth in claim 1 and further comprising: forming a non-ohmic device that is electrically in series with the CMO and the reactive metal, the non-ohmic device including a second non-linear I-V characteristic that is different than the first non-linear I-V characteristic.

14. The method as set forth in claim 13 , wherein the forming includes

depositing at least one layer of an insulating material and

depositing at least one layer of a conductive material such that the non-ohmic device comprises a metal-insulator-metal structure.

15. The method as set forth in claim 1 and further comprising: improving a switching characteristic of the memory element by treating at least one layer of material after the at least one layer of material has been deposited, the treating is operative to form an integrated non-ohmic device that is electrically in series with the CMO and the reactive metal, and the integrated non-ohmic device including a second non-linear I-V characteristic that is different than the first non-linear I-V characteristic.

16. The method as set forth in claim 1 , wherein the first electrode comprises multiple layers of electrically conductive thin-film materials.

17. The method as set forth in claim 16 , wherein at least one of the multiple layers of electrically conductive thin-film materials comprises a conductive oxide.

18. The method as set forth in claim 1 , wherein the second electrode comprises multiple layers of electrically conductive thin-film materials.

19. The method as set forth in claim 18 , wherein at least one of the multiple layers of electrically conductive thin-film materials comprises a conductive oxide.

Assignments (5)
NUNC PRO TUNC ASSIGNMENT Recorded Jun 21, 2018
From: UNITY SEMICONDUCTOR CORPORATION
To: HEFEI RELIANCE MEMORY LIMITED
Reel/Frame 046407/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2018
From: RAMBUS INC.
To: HEFEI RELIANCE MEMORY LIMITED
Reel/Frame 045984/0845 →
RELEASE Recorded Apr 9, 2012
From: SILICON VALLEY BANK; GOLD HILL CAPITAL
To: UNITY SEMICONDUCTOR, INC.
Reel/Frame 028132/0675 →
SECURITY AGREEMENT Recorded Apr 13, 2009
From: UNITY SEMICONDUCTOR CORPORATION
To: GOLD HILL CAPITAL
Reel/Frame 023129/0669 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2008
From: RINERSON, DARRELL, MR.; CHEVALLIER, CHRISTOPHE, MR.; HSIA, STEVE KUO-REN; KINNEY, WAYNE; LONGCOR, STEVEN W.; SANCHEZ, JOHN E., JR.; SWAB, PHILIP F.S.; WARD, EDMOND R.
To: UNITY SEMICONDUCTOR CORPORATION
Reel/Frame 021779/0183 →